Critical Link, LLC
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FEATURES
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TI TMS320C6711 Digital Signal
Processor
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200 MHz
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Hardware Floating Point Unit
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64 KB L2 cache
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2 Integrated McBSPs
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JTAG Emulation/Debug
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On-Board Xilinx FPGA
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XC3S400
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300 MHz Clock Logic
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288 KBits Block RAM
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3,584 Slices
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JTAG Interface/Debug
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8 MB CPU SDRAM
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2 MB NOR FLASH
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Standard SO-DIMM Interface
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100 FPGA User I/O Pins
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2 McBSP Interfaces
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DSP Emulator Interface
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FPGA JTAG Interface
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3.3, 2.5, 1.23 V Power Interface
MityDSP
MityDSP Processor Card
28-AUG-2007
APPLICATIONS
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Embedded Instrumentation
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Rapid Development / Deployment
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Embedded Digital Signal Processing
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Industrial Instrumentation
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Medical Instrumentation
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Embedded Control Processing
(actual size)
DESCRIPTION
The MityDSP is a highly configurable, very small form-factor processor card that
features a Texas Instruments TMS320C6711 200 MHz Digital Signal Processor (DSP)
tightly integrated with a Xilinx XC3S400 Spartan Field Programmable Gate Array
(FPGA), FLASH and SDRAM memory subsystems. Both the DSP and the FGPA are
capable of loading/executing programs and logic images developed by end users. The
MityDSP provides a complete digital processing infrastructure necessary for embedded
applications development.
Users of the MityDSP are encouraged to develop applications and FPGA firmware using
the MityDSP hardware and software development kit provided by Critical Link LLC.
The development kit includes API libraries compatible with the TI Code Composer
Studio compiler as well as FPGA netlist components compatible with the Xilinx ISE
FPGA synthesis tool. The libraries provide the necessary functions needed to configure
the MityDSP, program standalone MityDSP embedded applications, and interface with
the various hardware components on the board. In addition, the libraries include several
interface “cores” – FPGA and DSP software modules designed to interface with various
data converter modules (ADCs, DACs, LCD interfaces, etc) – as well as bootloading and
FLASH programming utilities.
Figure 1 provides a top level block diagram of the MityDSP processor card. As shown
in the figure, the primary interface to the MityDSP is through a standard SO-DIMM card
edge interface. The interface provides power, DSP emulator, FPGA JTAG, synchronous
serial connectivity, and up to 100 pins of configurable FPGA I/O for application defined
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MityDSP
MityDSP Processor Card
28-AUG-2007
interfacing. Details of the SO-DIMM connector interface are included in the SO-DIMM
Interface Description, below.
Figure 1 MityDSP Block Diagram
FPGA Bank I/O
The MityDSP provides 100 lines of FPGA I/O directly to the SO-DIMM card edge
interface. The 100 lines of FPGA I/O are distributed across TBD banks of the FPGA.
These I/O lines and their associated logic are completely configurable within the FPGA,
although typically a minimum of 2 lines are reserved for providing interface circuitry for
field FLASH upgrades.
With the Xilinx Spartan series of FPGA, a bank may be configured to operate on a
different electrical interface standard based on input voltage and termination
configurations. Of the 100 pins, 80 of the pins have been configured to use 3.3 Volt
CMOS level logic. The remaining 20 pins, located on bank 7 of the FPGA, have been
routed as differential pairs and may be configured as single ended 3.3 Volt or 2.5 Volt
CMOS level logic, or may be configured as 2.5 Volt LVDS pairs. The configuration
option is accomplished via resistor population on the board. Default configuration is for
3.3 Volt CMOS level logic. For pre-configured 2.5 Volt logic, please contact Critical
Link sales representatives.
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Bank I/O
(2.5 LVDS or 3.3 V CMOS)
Bank I/O (3.3 V LVCMOS)
JTAG/Emulator
McBSP 1
McBSP 2
ClkOut
Reset
1.23 V
3.3 V
2.5 V
GND
JTAG
Critical Link, LLC
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MityDSP
MityDSP Processor Card
28-AUG-2007
The FPGA Bank I/O provides optional pull-up and pull-down resistors for single ended
configuration. For LDVS pairs, termination resisters have been added to support
enabling of 100 Ohm DCI termination. Refer to the Xilinx Spartan 3 users guide for
more information.
Integrated DSP Serial Communications Modules
The C6711 processor includes two multichannel buffered serial ports (McBSPs) which
have been routed directly to the SO-DIMM interface. Both Critical Link (as part of the
MityDSP development kit) and TI provide several McBSP interface libraries for
integration with various data acquisition modules.
EMIF Interface / System Memory
The C6711 DSP and the Spartan FPGA are connected using the DSP External Memory
Interface (EMIF). The EMIF interface includes 4 chip select spaces. The EMIF interface
supports multiple data width transfers and bus wait state configurations based on chip
select space. 8, 16, and 32 bit data word sizes may be used. Two of the four chip select
lines (CE2, CE3) are reserved for the FPGA interface. The MityDSP also includes 4
lines between the FPGA and the C6711 for the purposes of generating interrupt signals.
In addition to the FPGA, 2 MB of on-board NOR FLASH memory and 8 MB of SDRAM
are connected to the DSP using the EMIF bus. The FLASH memory is 8 bits wide and is
connected to third chip select line of the EMIF (CE1). The FLASH memory is typically
used to store the following types of data:
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secondary bootloader DSP software
FPGA bootloader images
application DSP software
application DSP images
application data (non-volatile storage)
The C6711 DSP EMIF interface is capable of addressing 1 MB of data on the EMIF
interface. In order to provide access to the remaining 1 MB of FLASH memory, the
upper address line of the FLASH is controlled by Bank Control logic. Upon reset the
Bank Control Logic defaults to bank zero for bootloading support. Following
bootloading, the bank control logic is controlled by the FPGA. Refer to the MityDSP
User’s Guide for more information on bank control logic.
The SDRAM memory is 32 bits wide and is connected to the fourth chip select line of the
EMIF (CE0). The SDRAM provides an application user with program and data storage
space beyond the 64 KB of internal SRAM available in the C6711 processor. The
SDRAM / EMIF may be clocked at rates up to 100 MHz, supporting burst transfer data
rates of 400 MB per second.
The TI C6711 processor includes 64 KB of internal SRAM memory. The SRAM may be
configured as programmable RAM or as level 2 (L2) cache. The C6711 processor also
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MityDSP
MityDSP Processor Card
28-AUG-2007
provides 2 KB of level 1 (L1) data and instruction caching. Full DMA transfer between
internal memory and SDRAM is supported in the architecture.
Debug Interface
Both the JTAG interface signals for the FPGA and the JTAG and emulator signals for the
C6711 processor have been brought out to the SO-DIMM card edge interface to support
in-circuit debugging. The JTAG chains are separate on the interface. With an
appropriate break-out cable, the interface will support the use of standard Xilinx Platform
JTAG cable programming and the Spectrum Digital processor emulator (or equivalent).
Details of the pin-outs for the debug header are included in the Debug Interface
Description, below.
Growth Options
The MityDSP has been designed to support several upgrade options listed in the table
below. For ordering information and details regarding these options, please contact a
Critical Link sales representative.
Option / Part
MityDSP – Industrial Temp Grade
MityDSP – XM
Description
Industrial temperature range (-40 to 70 C), TI TMS320C6711
CPU speed grade approved for 150 MHz operation.
FPGA Upgraded to XS3C1000
SDRAM Upgraded to 32 MBytes
FLASH Upgraded to 16 MBytes
MityDSP-XM, industrial temperature range (-40 to 70 C), TI
TMS320C6711 CPU speed grade approved for 150 MHz
operation.
MityDSP – XM Industrial Temp
Grade
Example Application
The figure below illustrates an example application utilizing the MityDSP processor card.
The application requires modulating a laser drive with an excitation signal, capturing the
results from a photo-detector and applying a lock-in detector circuit in order to detect
signals of interest. In addition, several low speed thermal and pressure sensors are
monitored and used to control system cooling and mass flow control devices.
The system provides standard RS-232 interfaces for integrating with off-the-shelf flow
control and temperature control devices. The system also requires a USB interface to
support direct PC communications and also requires an Ethernet interface to support
remote access.
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MityDSP
MityDSP Processor Card
28-AUG-2007
Figure 2 Typical MityDSP Application
In this application, the developer need only focus on the interface circuitry – signal
conditioning, ADC selection, communications I/O – as the processing platform design is
complete within the MityDSP. The engineer is able to interface directly to the selected
DACs and ADCs by connecting them to the Bank I/O on the FPGA and utilizing the
MityDSP hardware and software development kit APIs. Waveform generation,
synchronization, and Lock-In processing can be implemented directly in the FPGA or
divided between the FPGA and the DSP according to design requirements.
The same design approach is accomplished for the USB, network, and RS-232
communications links. The MityDSP developer’s kit provides standard UART
interfaces, a 10/100 EMAC, and includes a port of the LwIP TCP/IP layer stack for the
MityDSP C6711.
This approach minimizes the design time required (in application software, FPGA
firmware, and PCB design) for system infrastructure and allows focusing on the
application specific requirements.
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