UM10850
LPC5410x User manual
Rev. 2.5 — 25 April 2017
User manual
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Abstract
Content
LPC5410x, ARM Cortex-M4, ARM Cortex-M0+, microcontroller, sensor
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LPC5410x User Manual
NXP Semiconductors
UM10850
LPC5410x User manual
Revision history
Rev
2.5
Date
20170425
Description
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Updated
Table 253 “Register overview: State Configurable Timer SCT/PWM (base address
0x1C01 8000)”:
fixed the base address.
Added a Remark to
Section 25.7.1.1 “Rate calculations”
and
Table 417 “Settings for 400 KHz clock
rate”.
Updated
Table 456 “Transmit data register for SPIn (TXDATCTLSPI[0:1], address offset
[0x2018:0x2118]) bit description”
and
Table 372 “SPI Transmitter Data and Control register
(TXDATCTL, offset 0x18) bit description”:
Changed description of Bit 22 to: Read received data.
Received data must be read first and then TxDATA should be written to allow transmission to
progress for non DMA cases. In slave mode, an overrun error occurs if received data is not read
before new data is received.
Added text:
On power-up, the BOD is enabled. Power API disables BOD in deep-sleep
mode. User must disable BOD reset (bit 2 in the BODCTRL register) and clear bit ‘6’ in
the BODCTRL register before calling the power API to enter deep-sleep mode to
Section 7.3.4.2 “Programming Deep-sleep mode”.
Updated
Table 151 “Register overview: I/O configuration (base address 0x4001 C000)”.
Name:
PIO0_[0:3] and Description: Digital I/O control for port 0 pins PIO0_0 to PIO0_3.
Updated
Table 278 “SCT event control register 0 to 12 (EV[0:12]_CTRL, offset 0x304 (EV0_CTRL)
to 0x364 (EV12_CTRL)) bit description”.
Bits 9:6, IOSEL description text: Selects the input or
output signal associated with this event (if any). If CKMODE is 1x, the input that is used as the
clock may not be selected to trigger events.
Updated Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124)
bit description”: Changed the system clock rates of the following:
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2 system clocks flash access time (for system clock rates up to 24 MHz).
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3 system clocks flash access time (for system clock rates up to 48 MHz).
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4 system clocks flash access time (for system clock rates up to 72 MHz).
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5 system clocks flash access time (for system clock rates up to 84 MHz).
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Added 0x5, 6 system clocks flash access time (for system clock rates up to 100 MHz).
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2.4
20160913
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2.3
20160906
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Added text and a remark to Section 30.1 “How to read this chapter”.
Added a remark to Section 30.3 “General description”.
Added text and a remark to Section 30.4 “API description”.
Added Table 466 “Power API calls in LPCOpen power library”.
Renamed section 30.4.1 to Section 30.4.1 “Chip_POWER_SetPLL”.
Renamed section 30.4.2 to Section 30.4.2 “Chip_POWER_SetVoltage”.
Deleted Param0: mode and Low power mode; was section 30.4.2.1.
Added Section 30.4.3 “Chip_POWER_EnterPowerMode”.
Updated Section 30.5 “Functional description”.
UM10850
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 2.5 — 25 April 2017
2 of 465
NXP Semiconductors
UM10850
LPC5410x User manual
Revision history
…continued
Rev
2.2
Date
20160331
Description
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Removed Section 4.5.51: Device ID1 register values and moved Table 89 “Device ID1 register
values” to section Section 4.5.50 “Device ID1 register”.
Removed IrDA mode from Section 21.5 “General description” in Chapter 21 “LPC5410x USARTs
(USART0/1/2/3)”.
Updated Table 307 “USART Configuration register (CFG, offset 0x00) bit description”. Removed
IOMODE from the table.
Removed the section: IrDA communication in Chapter 21 “LPC5410x USARTs (USART0/1/2/3)”.
Added the sentence to Section 22.5 “General description”: Set the RXIGNORE bit to only transmit
data and not read the incoming data. Otherwise, the transmit halts when the receiver buffer is full.
Added the sentence to Table 328 “SPI Transmitter Data and Control register (TXDATCTL, offset
0x18) bit description”, bit 22, RXIGNORE: The SPI collects receive data, according to SPI clocking,
unless RXIGNORE is set; 0: The SPI transmit halts when the receive data FIFO is full.
Added the sentence to Section 22.7.7 “Data stalls”: The transmitter will be stalled until data is read
from the receive FIFO. Use the RXIGNORE control bit setting, to avoid the need to read the
received data.
UM10850
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 2.5 — 25 April 2017
3 of 465
NXP Semiconductors
UM10850
LPC5410x User manual
Revision history
…continued
Rev
2.1
Date
20151218
Description
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Added Table 89 “Device ID1 register values”.
Added text to Section 4.5.47.1 “CPU Control register”: The user can assign Cortex-M0+ to be the
master CPU via this register if needed after it is brought out of reset by Cortex-M4.
Added text to Section 4.6.3 “Brown-out detection”: On the LPC5410x, the BOD is enabled by
default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory
trimming applied. In the BOD block the interrupt portion is turned off and only the reset portion is
on. After POR/BOD resets, the BootROM takes over and applies the factory BOD trim value so
that the trip points become accurate. See the LPC5410x data sheet for BOD interrupt/reset voltage
levels in the BOD static characteristics.
Added section Section 12.5.7 “Channel chaining”.
Updated Figure 53 “System FIFO conceptual block diagram”.
Updated description of 15:12,TIMEOUT VALUE; Specifies the maximum time value for timeout at
the timer position identified by TimeoutBase. Minimum time TimeoutValue - 1 (clocks of wdt_clk).
See Table 383 “Configuration register for USARTn (CFGUSART[0:3], address offset
[0x1000:0x1300]) bit description”.
Updated the values in the sentence: TimeoutValue can be any value from 2 to 15. This gives a
maximum timeout range of 2 counts (too small to be useful) at the bottom end, up to 15 * 32,768
(491,520) counts at the upper end. See Section 24.5.7.1 “Receiver Timeout”
Updated text in Table 468 “set_voltage routine”: Param1: desired frequency (in Hz); was: Param1:
desired frequency (in MHz).
Removed text from Section 5.2 “General description”, list 3:
...or for monitoring analog inputs (comparators and internal voltage reference and temperature
sensor via one of the comparators).
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Removed comparator from Section 13.5 “General description”: This provides an extremely
powerful control tool - particularly when the SCT inputs and outputs are connected to other on-chip
resources (ADC triggers, other timers etc.) in addition to general-purpose I/O.
Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and
set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.4.2
“Programming Deep-sleep mode”.
Added AHBCLKDIV register should be set to 1 in: List item 2 “Select the IRC as the main clock and
set the AHBCLKDIV register to 1. See Table 45, Table 46, and Table 58.”, Section 5.3.5.2
“Programming Power-down mode”.
Added registers, DIRSET0, DIRCLR0, DIRNOT0. See Table 134 “Register overview: GPIO port
(base address 0x1C00 0000)” and Section 9.5.10 “GPIO port direction set registers”,
Section 9.5.11 “GPIO port direction clear registers”, and Section 9.5.12 “GPIO port direction toggle
registers”.
Added note to Table 223 “SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit
description” and Table 224 “SCT DMA 1 request register (DMAREQ1, address 0x5000 4060) bit
description”.
Added remark to Section 4.5.37.5.1 “System PLL spread spectrum control register 0”: If the 32 kHz
RTC oscillator is used as the reference input to the PLL, then use fixed values SELI=1, SELP=6
and SELR=0, instead of applying the above rules. These values reduce the PLL loop bandwidth to
combat the effect of reference oscillator jitter on the PLL output signal.
In Table 62 “Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit
description” replaced offset in table title to address 0x4000 0124.
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UM10850
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 2.5 — 25 April 2017
4 of 465
NXP Semiconductors
UM10850
LPC5410x User manual
Revision history
…continued
Rev
2.1
Date
Description
•
•
Added text to Section 17.2 “Features”: 24-bit interrupt timer clocked from CPU clock.
Added address to Section 31.3.7.3 “RAM used by IAP command handler”’: Flash programming
commands use the top 32 bytes of on-chip SRAM0, 0x0200 FFE0 - 0x0200 FFFF (see Section
2.1.1 for details of the SRAM configuration). The maximum stack usage in the user allocated stack
space is 128 bytes and grows downwards.
Removed Receiver Idle from Section 21.2 “Features” and replaced with Transmitter Idle.
Added the text receiver to List item • “A receiver timeout feature (for USART and SPI) provides a
means to get data left for a time in a FIFO that has not reached its threshold to be transferred.” in
Section 24.3 “Features”.
Added List item • “Timeouts: The watchdog oscillator must run for the UART and SPI timeout
counter to work. Enable the watchdog oscillator via the PDRUNCFG register (Table 72).” to the
Section 24.2 “Basic configuration”.
Added text, The source of the timeout clock is the watchdog oscillator with a nominal frequency of
500 kHz to Section 24.5.7.1 “Receiver Timeout”, and Section 24.5.15.1 “Receiver Timeout”.
Added text to Section 21.5 “General description”: The USART receiver timeout feature can also be
used to identify the USART receiver idle state. Set the bit TIMEOUTCONTONEMPTY in the
respective CFGUSART register to 1 to allow the timeout to flag idle state of the USART peripheral.
Fixed the reset value of MSTTIME (Master timing configuration); was 0x77, now 0x56. See
Table 340 “Register overview: I2C0/1/2 (register base addresses 0x4009 4000 (I2C0),
0x4009 8000 (I2C1), 0x4009 C000 (I2C2))”.
Added the Flash Management Registers FMSSTART and FMSSTOPUpdated to Chapter 28
“LPC5410x Flash signature generator”.
Typographic errors have been corrected and minor pieces of information added or clarified
throughout the document.
Registers supporting use of dual processors on LPC54102 devices has been added to the Syscon
chapter.
A Power Management chapter has been added.
Some pins in the Pin description chapter have the type changed to Z for open drain pins.
A section has been added to the ADC chapter describing how to configure sample times for
different conversion configurations.
The ADC operating speed is increased to 5 Ms/s.
Updated Section 4.5.33 “Flash configuration register” text and Table 62.
Typographic errors have been corrected and minor pieces of information added or clarified
throughout the document.
In the NVIC chapter, the bit numbers for the priority register fields have been corrected.
In the Syscon chapter, a functional description section has been added following the register
descriptions to provide additional information about some functions.
The SCTimer/PWM chapter has been revised to better explain the function.
Description of the ISP-AP interface and commands is added to the Debug chapter.
References to Timer 0, 1, 2, 3, and 4 have been updated to use the terminology of the Standard
counter/timers chapter (CT32B0, 1, 2, 3, 4).
Typographic errors have been corrected and minor pieces of information added or clarified
throughout the document.
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2.0
20150410
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1.1
20141121
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UM10850
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 2.5 — 25 April 2017
5 of 465
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