19-4018; Rev 0; 3/06
MAX1217/MAX1218/MAX1219 Evaluation Kits
General Description
The MAX1217/MAX1218/MAX1219 evaluation kits (EV kits)
are fully assembled and tested circuit boards that contain
all the components necessary to evaluate the perfor-
mance of the MAX1217/MAX1218/MAX1219 dual, 12-bit,
125Msps/170Msps/210Msps analog-to-digital converters
(ADCs). These ADCs accept differential analog inputs,
which the EV kit generates from user-provided single-
ended input sources. The digital outputs produced by the
ADC can be easily sampled using a high-speed logic
analyzer or data-acquisition system. The EV kit operates
from 1.8V/3.3V power supplies and includes circuitry that
generates a differential clock signal from a single-ended
AC source provided by the user.
♦
Low Voltage and Power Operation
♦
On-Board Clock-Shaping Circuitry
♦
On-Board LVDS/LVPECL Differential Level
Translators
♦
Fully Assembled and Tested
Features
♦
ADC Sampling Rates from 125Msps to 210Msps
Evaluate: MAX1217/MAX1218/MAX1219
Ordering Information
PART
MAX1217EVKIT
MAX1218EVKIT
MAX1219EVKIT
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
IC PACKAGE
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
EV Kit Specific Component List
EV KIT PART
NUMBER
MAX1217EVKIT
MAX1218EVKIT
MAX1219EVKIT
U1
DESIGNATION
DESCRIPTION
Maxim MAX1217ECQ
(100-pin TQFP)
Maxim MAX1218ECQ
(100-pin TQFP)
Maxim MAX1219ECQ
(100-pin TQFP)
Part Selection Table
PART
MAX1219ECQ
MAX1218ECQ
MAX1217ECQ
SPEED (Msps)
210
170
125
Common Component List
DESIGNATION
C1, C3, C5, C6,
C12, C13, C18,
C42, C43
C2, C4,
C115–C123
C7, C19, C20,
C33–C41,
C112, C113,
C114
C14–C17
C21–C32,
C108–C111
C44–C70
QTY
9
DESCRIPTION
0.1µF ±20%, 25V X7R ceramic
capacitors (0603)
TDK C1608X7R1E104M
0.1µF ±20%, 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
0.1µF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
2.0pF ±0.25pF, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H2R0C
0.01µF ±5%, 25V C0G ceramic
capacitors (0603)
TDK C1608C0G1E103J
0.01µF ±10%, 25V X7R ceramic
capacitors (0402)
TDK C1005X7R1E103K
DESIGNATION
C71–C74
C76–C79
C81–C84
C86–C89,
C91–C103
C104–C107
J1, J3, J7, J15
J5, J6, J14
J8, J10, J11, J13
J9, J12
J16, J18
J17
JU1, JU2
QTY
4
0
4
DESCRIPTION
220µF ±20%, 6.3V tantalum
capacitors (C-case)
AVX TPSC227M006R0250
Not installed (C-case)
10µF ±20%, 6.3V X5R ceramic
capacitors (0805)
TDK C2012X5R0J106M
1.0µF ±20%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105M
4.7µF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J475M
SMA PC mount connectors
2-pin headers
Dual-row, 50-pin headers
Dual-row, 6-pin headers
Triple-row, 75-pin headers
Triple-row, 9-pin header
Jumpers, dual-row, 8-pin headers
11
15
17
4
4
4
3
4
2
2
1
2
16
27
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX1217/MAX1218/MAX1219 Evaluation Kits
Evaluate: MAX1217/MAX1218/MAX1219
Common Component List (continued)
DESIGNATION
JU3–JU8
R1, R3,
R23–R26, R121,
R148, R151, R152
R2, R4, R5–R10,
R13–R18,
R112, R113, R150
R19–R22
R27–R107
R108–R111
R114
R115
R116
R117, R118
R119, R120
QTY
6
10
DESCRIPTION
Jumpers, 3-pin headers
49.9Ω ±1% resistors (0603)
DESIGNATION
R122–R147, R153
R149, R156
R154, R155
T1–T4
0
Not installed (0603)
TP1–TP6
4
81
4
1
1
1
2
2
24.9Ω ±0.1% resistors (0603)
Vishay/Dale TNPW060324R9BEEA
IRC PFC-W0603R-02-24R9-B
49.9Ω ±1% resistors (0402)
10Ω ±0.1% resistors (0603)
Vishay/Dale TNPW060310R0BEEA
4.02kΩ ±1% resistor (0603)
2kΩ ±1% resistor (0603)
5kΩ potentiometer, 19-turn, 3/8in
13.0kΩ ±1% resistors (0603)
100kΩ potentiometers, 19-turn, 3/8in
Y1
—
—
0
8
1
U1
U2
6
1
1
QTY
27
2
0
4
DESCRIPTION
100Ω ±1% resistors (0603)
510Ω ±5% resistors (0603)
Not installed (T93YB)
1:1, 800MHz RF transformers
Mini-Circuits ADT1-1WT
Test points (black)
Note:
See the
EV Kit Specific
Component List
Maxim MAX9388EUP (20-pin TSSOP)
3.3V, ECL, quad differential
receivers (SO-20)
On Semiconductor
MC100LVEL17DW
Not installed (VF561E)
Shunts
MAX1217/MAX1218/MAX1219
PC board
U3–U9
7
Component Suppliers
SUPPLIER
AVX
IRC
Mini-Circuits
TDK
Vishay
PHONE
843-946-0238
361-992-7900
718-934-4500
847-803-6100
402-564-3131
FAX
843-626-3123
361-992-3377
718-332-4661
847-390-4405
402-563-6296
WEBSITE
www.avxcorp.com
www.irctt.com
www.minicircuits.com
www.component.tdk.com
www.vishay.com
Note:
Indicate that you are using the MAX1217/MAX1218/MAX1219 when contacting these component suppliers.
Quick Start
Recommended Equipment
•
DC power supplies:
Analog (AVCC)
1.8V, 1A
Output drive (OVCC)
1.8V, 250mA
Clock (VCLK)
3.3V, 100mA
Buffer (VPECL)
3.3V, 1A
Signal generator with low phase noise and low jitter
for clock input (e.g., HP/Agilent 8644B)
Two signal generators for analog signal inputs
(e.g., HP/Agilent 8644B)
Logic analyzer or data-acquisition system
(e.g., HP/Agilent 16500C, TLA621)
•
•
Analog bandpass filters (e.g., Allen Avionics, K&L
Microwave) for input signal and clock signal
Digital voltmeter
Procedure
The MAX1217/MAX1218/MAX1219 EV kits are fully
assembled and tested surface-mount boards. Follow
the steps below for board operation.
Do not turn on
power supplies or enable function generators until
all connections are completed.
1) Verify that shunts are installed in the following locations:
JU1 (3-4)
→
Internal reference enabled (channel A)
JU2 (3-4)
→
Internal reference enabled (channel B)
JU3 (2-3)
→
Channel A output in two’s-comple-
ment format
•
•
•
2
_______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
JU4 (2-3)
→
Channel B output in two’s-comple-
ment format
JU5 (1-2)
→
Divide-by-two clock disabled
JU6, JU7 (2-3)
→
Variable duty-cycle input selected
2) Connect a 1.8V, 1A power supply to AVCC.
Connect the ground terminal of this supply to GND.
3) Connect a 1.8V, 250mA power supply to OVCC.
Connect the ground terminal of this supply to GND.
4) Connect a 3.3V, 100mA power supply to VCLK.
Connect the ground terminal of this supply to GND.
5) Connect a 3.3V, 1A power supply to VPECL.
Connect the ground terminal of this supply to GND.
6) Connect the clock signal generator to the input of
the clock bandpass filter.
7) Connect the output of the clock bandpass filter to
the EV kit SMA connector labeled J7. Monitor the
clock signal using a differential oscilloscope probe
at connector J14.
8) Connect the first analog signal generator to the
input of the desired bandpass filter.
9) Connect the output of the first bandpass filter to the
EV kit SMA connector labeled J1.
10) Connect the second analog signal generator to the
input of the desired bandpass filter.
11) Connect the output of the second bandpass filter to
the EV kit SMA connector labeled J3.
12) Ensure that all signal generators are phase-locked
to a common reference frequency.
13) Connect the logic analyzer to either headers J8 to
J10 (LVDS-compatible signals), J11 to J13
(LVPECL-compatible signals), or J16 to J18 (single-
ended capture). See the
Output Bit Locations
sec-
tion for header descriptions and connections.
14) Turn on all the power supplies.
15) With a voltmeter, verify that 1.32V is measured
across test points TP3 and TP4. If the voltage is not
1.32V, adjust potentiometer R116 until 1.32V is
obtained.
16) Enable the function generators.
17) Set the clock signal generator to output a 210MHz
signal. The amplitude of the generator should be
sufficient to produce a 13.8dBm (1.09V
P-P
) signal
at the SMA input of the EV kit. Insertion losses due
to the series-connected filter (step 7) and the inter-
connecting cables decrease the amount of power
seen at the EV kit input. Account for these losses
when setting the signal generator amplitude.
18) Set the analog input signal generators to output the
desired test frequency. The amplitude of the gener-
ator should produce a signal that is no larger than
11dBm (793mV
P-P
) as measured at the SMA input
of the EV kit. Insertion losses due to the series-con-
nected filter (steps 8 and 10) and the interconnect-
ing cables decrease the amount of power seen at
the EV kit input. Account for these losses when set-
ting the signal generator amplitude.
19) Enable the logic analyzer.
20) Collect data using the logic analyzer.
Evaluate: MAX1217/MAX1218/MAX1219
Detailed Description
The MAX1217/MAX1218/MAX1219 EV kits are fully
assembled and tested circuit boards that contain all the
components necessary to evaluate the performance of
the MAX1217/MAX1218/MAX1219 dual, 12-bit parallel
output ADCs.
The MAX1217/MAX1218/MAX1219 accept differential
inputs; however, on-board transformers (T1, T3) con-
vert readily available single-ended source outputs to
the required differential signals. Measure the inputs of
the MAX1217/MAX1218/MAX1219 at headers J5 and
J6 using a differential oscilloscope probe.
Output level translators (U3–U8) buffer and convert the
LVDS output signals of the MAX1217/MAX1218/MAX1219
to higher-voltage LVPECL signals, which can be captured
by a wide variety of logic analyzers. The LVDS outputs
are accessed at headers J8, J9, J10. The LVPECL out-
puts are accessed at headers J11, J12, J13. Additionally,
the LVPECL outputs can be captured with a single-ended
logic-analyzer probe at headers J16, J17, and J18.
The EV kit is designed as a four-layer PC board to opti-
mize the performance of the MAX1217/MAX1218/
MAX1219. Separate analog, digital, clock, and buffer
power planes minimize noise coupling between analog
and digital signals. 50Ω coplanar transmission lines are
used for analog and clock inputs. 100Ω-differential
coplanar transmission lines are used for all digital LVDS
outputs. All differential outputs are properly terminated
with 100Ω termination resistors between true and com-
plementary digital outputs. The trace lengths of the
100Ω-differential LVDS lines are matched to within a
few thousandths of an inch to minimize layout-depen-
dent data skew.
Power Supplies
The MAX1217/MAX1218/MAX1219 EV kits require sep-
arate analog, output-drive, clock, and buffer power
supplies for best performance. Two 1.8V power sup-
plies are used to power the analog (AVCC) and output-
driver (OVCC) circuitry of the MAX1217/MAX1218/
3
_______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
Evaluate: MAX1217/MAX1218/MAX1219
MAX1219. The clock circuitry (VCLK) is powered by a
3.3V power supply. A separate 3.3V power supply
(VPECL) is used to power the output buffers (U3–U9) of
the EV kit.
crystal oscillator. To use this function, install a three-pin
header at location JU8. Also, install a crystal oscillator with
the desired frequency at location Y1.
Jumper JU8 controls the enable function of the oscilla-
tor. See
Table
3 for shunt settings. To improve perfor-
mance of the EV kit, disable the crystal oscillator when
not in use.
Clock
The MAX1217/MAX1218/MAX1219 EV kits feature a
variety of clock input methods. A differential clock signal
can be generated from a single-ended sine wave
applied to J15. A variable-duty-cycle differential clock
signal can be generated from a single-ended sine wave
applied to J7 (see the
Variable-Duty-Cycle Clock-
Shaping Circuit
section). Alternatively, the on-board
crystal oscillator can be utilized instead of a user-pro-
vided signal source (see the
On-Board Crystal Oscillator
section). U2 multiplexes all three of these inputs onto
the MAX1217/MAX1218/MAX1219 clock input lines.
Jumpers JU6 and JU7 control the multiplexer. See
Table
1 for shunt settings.
Table 3. Crystal Oscillator Shunt Settings
(JU8)
SHUNT POSITION
1-2
2-3*
DESCRIPTION
Crystal oscillator enabled.
Crystal oscillator disabled.
*Default
configuration: JU8 (2-3).
Table 1. Clock Multiplexer Shunt Settings
(JU6, JU7)
JUMPER
JU6
SHUNT POSITION
2-3*
JU7
2-3*
Variable-duty-cycle clock selected.
Apply a signal to J7. Measure the duty
cycle at J14.
Differential clock signal selected.
Apply a signal to J15.
Clock disabled.
On-board crystal oscillator selected.
Enable crystal using JU8.
DESCRIPTION
Variable-Duty-Cycle Clock-Shaping Circuit
A differential multiplexer (U2) processes the single-
ended sine wave (applied at J7) and generates the
required differential clock signal. The clock signal’s duty
cycle can be adjusted with potentiometer R116. A clock
signal with a 50% duty cycle (recommended setting)
can be achieved by adjusting R116 until 1.32V is pro-
duced across test points TP3 and TP4 when the clock
voltage supply (VCLK) is set to 3.3V. Measure the clock
signal with a differential oscilloscope probe at J14.
Input Signal
The MAX1217/MAX1218/MAX1219 accept differential
analog input signals; however, the EV kits only require
a single-ended analog input signal, with an amplitude
of less than 11dBm (793mV
P-P
) provided by the user.
On-board transformers (T1, T3) convert the single-
ended analog inputs and generate differential analog
signals at the ADC’s differential input pins.
1-2
2-3
1-2
1-2
1-2
2-3
*Default
configuration: JU6 (2-3), JU7 (2-3).
Reference Voltage
There are three methods to set the full-scale range of the
MAX1217/MAX1218/MAX1219. The EV kits can be con-
figured to use the MAX1217/MAX1218/MAX1219’s inter-
nal reference, a stable low-noise external reference, or
the on-board reference adjustment circuitry.
The MAX1217/MAX1218/MAX1219 feature an internal
1.23V bandgap reference circuit, which, in combination
with an internal reference-scaling amplifier, determines
the full-scale range of the MAX1217/MAX1218/MAX1219.
To compensate for gain errors or increase/decrease the
ADC’s full-scale range, the voltage of this bandgap refer-
ence can be indirectly adjusted by configuring JU1/JU2
and adjusting potentiometer R119/R120 on the
MAX1217/MAX1218/MAX1219 EV kits. Connecting a
potentiometer between REFADJ and REFIO increases
the full-scale range of the ADC. Conversely, connecting
the potentiometer between REFADJ and GND decreases
Divide-by-Two Clock
The MAX1217/MAX1218/MAX1219 feature internal
divide-by-two clock circuitry. Jumper JU5 controls this
function. See
Table
2 for shunt settings.
Table 2. Divide-by-Two Shunt Settings (JU5)
SHUNT
POSITION
1-2*
2-3
MAX1217/
MAX1218/MAX1219
CLKDIV PIN
AVCC
GND
DESCRIPTION
Clock signal is divided by 1.
Clock signal is divided by 2.
*Default
configuration: JU5 (1-2).
On-Board Crystal Oscillator
To facilitate easy evaluation, the MAX1217/MAX1218/
MAX1219 EV kits feature an open location for an on-board
4
_______________________________________________________________________________________
MAX1217/MAX1218/MAX1219 Evaluation Kits
the full-scale range. The MAX1217/MAX1218/MAX1219
feature two sets of pins to calibrate each channel
independently; thus, the MAX1217/MAX1218/MAX1219
EV kits feature two sets of reference circuitry. Jumper
JU1 and potentiometer R119 control the reference of
channel A. Jumper JU2 and potentiometer R120 control
the reference of channel B. See
Table
4 for shunt settings.
improve the dynamic performance of the device. In addi-
tion, seven drivers (U3–U9) buffer and level-translate the
ADC’s digital outputs to LVPECL-compatible signals.
The drivers increase the differential voltage swing, and
are able to support large capacitive loads, which may be
present at the logic analyzer connection. The outputs of
the buffers are connected to headers J11, J12, and J13.
See
Table
6 for bit location of headers J8–J13.
Evaluate: MAX1217/MAX1218/MAX1219
Table
4. Reference Shunt Settings (JU1, JU2)
SHUNT
POSITION
1-2
3-4*
5-6
7-8
DESCRIPTION
Internal reference disabled. Apply a
reference voltage at the REFIO pad.
Internal reference enabled.
REFADJ connected through potentiometer
R119/R120 to REFIO.
REFADJ connected through potentiometer
R119/R120 to GND.
Table
6. Output Bit Locations (Differential
Capture)
CHANNEL A
SIGNAL
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
UNBUFFERED = J8
BUFFERED = J11
1
2
5
6
9
10
13
14
17
18
21
22
25
26
29
30
33
34
37
38
41
42
45
46
49
50
UNBUFFERED
J9-3
J9-4
N: Complementary.
CHANNEL B
UNBUFFERED = J10
BUFFERED = J13
49
50
45
46
41
42
37
38
33
34
29
30
25
26
21
22
17
18
13
14
9
10
5
6
1
2
BUFFERED
J12-3
J12-4
OR
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
*Default
configuration: JU1 (3-4), JU2 (3-4).
Output Signal
The MAX1217/MAX1218/MAX1219 feature two, parallel
LVDS-compatible, digital output buses. Each output
bus transmits the digitized analog input signals of
channels A and B. An additional output (CLK) is provid-
ed for data synchronization. Refer to the MAX1217,
MAX1218, MAX1219 data sheets for more details.
Output Format
The digital output coding can be set to either two’s
complement or straight offset binary by configuring
jumper JU3 and JU4. Each channel can be set inde-
pendently. Jumper JU3 controls the output format of
channel A. Jumper JU4 controls the output format of
channel B. See
Table
5 for shunt positions.
Table
5. Output Format Shunt Settings
(JU3, JU4)
SHUNT
POSITION
1-2
2-3*
T/B
PIN
AVCC
GND
DESCRIPTION
Digital output in straight
offset binary format.
Digital output in two’s-
complement format.
*Default
configuration: JU3 (2-3), JU4 (2-3).
Output Bit Locations
The digital outputs of the MAX1217/MAX1218/MAX1219
are connected to headers J8, J9, and J10. PC board
trace lengths are matched to minimize data skew and
SIGNAL
P
CLK
N
P: True.
Note:
Requires differential logic analyzer.
5
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