VmodCAM™ Reference Manual
Revision:
July 19, 2011
Note:
This document applies to REV C of the board.
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Overview
The VmodCAM board provides digital imaging
capabilities for any Digilent FPGA system
board with a VHDCI connector. It features two
Aptina MT9D112 2-megapixel CMOS digital
image sensors. The sensors can provide frame
rates from 15 FPS upwards, depending on the
resolution.
Its system-on-a-chip design integrates an
image flow processor and enables selectable
output formats, scaling, and special effects.
The integrated PLL (phase-locked loop) and
microprocessor offer a flexible serial control
interface. The output data is sent on a parallel
bus in processed YCrCb, RGB, or raw Bayer
formats.
Features include:
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two independent Aptina MT9D112 2-
megapixel CMOS digital image sensors
1600x1200 maximum resolution at 15
FPS
63mm inter-camera spacing (stereo
baseline)
10-bit raw color depth
I
2
C control bus
Bayer, RGB, YCrCb output formats
automatic exposure, gain, and white
balance
powerful image correction algorithms
image scaling
output FIFO
68-pin female VHDCI connector
Each camera has a 2 megapixel color sensor
array in Bayer color filter arrangement. The
sensor readout is 10-bit and supports skipping
or binning rows/columns.
The integrated PLL can generate an internal
clock from the master clock and supports a
wide range of resolutions and frame rates.
The integrated image flow processor applies
correction algorithms to improve image quality.
It can process raw sensor data into RGB or
YCrCb output formats, and crop or scale the
image.
Since some of the processing algorithms
output data in bursts, the parallel output
interface can use a FIFO buffer to provide
constant data rate.
The camera also features a sequencer to
coordinate events triggered by the user.
Operation
The camera systems first need to be properly
configured. This includes not only setting
imaging parameters like resolution or output
format, but PLL configuration and
microprocessor sequencing too. The order in
which these steps are performed is very
important.
page 1 of 6
Functional Description
The two MT9D112 cameras can be controlled
independently and can acquire two separate,
simultaneous image feeds. They are controlled
by a two-wire interface.
Doc: 502-179
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VmodCAM Reference Manual
First, you must set up the power-up and reset
sequence. Then you need to understand the
control interface in order to configure the
cameras. The following sections describe this
in detail.
t1
t2
Power-Up and Reset Sequence
The VmodCAM should only be attached to the
system board once the signals driven by the
system board are defined.
The camera uses the analog and digital supply
voltage rails provided on-board. The power
supplies are on by default, but can be turned
off, by driving the VDD-EN signal low (see
Table 3.)
The power supplies are used by both cameras.
While the cameras do power-on reset
themselves, it’s always a good idea to do a full
reset as part of the controller routine.
t3
t6
t4
t5
Description
VDD-EN negative
pulse width
VDD-EN high to
first MCLK pulse
ROM read time
until first control
byte
Active MCLK
before/after #RST
edge
#RST negative
pulse width
Min
100
75
Max
Unit
ms
us
6000
MCLK
cycles
MCLK
cycles
MCLK
cycles
10
30
Table 1
Power-Up/Reset Timing
Control Interface
The two-wire serial interface (SDA, SCL) can
be used to control various parts of the camera.
The camera acts as a slave device.
A typical register write consists of:
Figure 1
Power-Up Sequence
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Figure 2
Reset Sequence
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start condition
8-bit device address (0x78 for the
MT9D112) + acknowledge bit
upper byte of 16-bit register address +
acknowledge bit
lower byte of register address +
acknowledge bit
upper byte of the 16-bit data +
acknowledge bit
lower data byte + acknowledge bit
stop condition.
The MCLK is important. If the PLL in the
camera is enabled, MCLK should be stable.
Stopping MCLK without respecting the reset
sequence might leave the camera in an
undefined state. This could be the case when
the FPGA is re-configured. Performing a
power-cycle in the first stages of the controller
is recommended.
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VmodCAM Reference Manual
A register read consists of:
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start condition
8-bit device address (0x78 for the
MT9D112) + acknowledge bit
upper byte of 16-bit register address +
acknowledge bit
lower byte of register address +
acknowledge bit
start condition
8-bit device address (0x79 for the
MT9D112) + acknowledge bit
upper byte of the 16-bit data +
acknowledge bit
lower data byte + no-acknowledge bit
stop condition.
power-on and reset sequences show, the
camera needs certain signals set and a
running MCLK before the two-wire interface is
enabled.
Once the necessary number of MCLK cycles
are provided, the following registers/variables
need to be read/written.
Identify the camera:
To verify that the camera is working, read
R[0x3000] to return 0x1580, which is the
device ID of the camera.
Reset the MCU:
1. R[0x3386] = 0x0501
2. R[0x3386] = 0x0500; release from reset
Set the PLL:
1. R[0x3214] = 0x0D85; this sets the slew
rate of the output pins
2. R[0x341E] = 0x8F0B; power-down and
bypass PLL; if you want to use MCLK
as the pixel clock, skip steps 3-5.
3. R[0x341C][13:8] = N
R[0x341C][7:0] = M;
Where PCLK = MCLK * M / (N+1) / 8.
For example, to obtain a pixel clock of
80MHz (maximum) from an MCLK of
24MHz, set M=80, N=2.
4. R[0x341E] = 0x8F09; power up PLL,
wait 1ms for the PLL to stabilize
5. R[0x341E] = 0x8F08; use PLL clock
instead of MCLK
Wake up from standby:
1. R[0x3202] = 0x0008
Insert image parameters:
You can change the image parameters to suit
your project. See the
Image Configuration
Example
below to insert an image parameter
configuration sequence.
page 3 of 6
There are two types of configuration controls,
hardware registers and driver variables. The
hardware registers usually control the sensor
and some other sub-systems, while the driver
variables sequence the on-chip
microprocessor. These two types of controls
are accessed differently.
Hardware registers are two-wire accessible,
meaning their address can be used directly in
the register address phase of the two-wire
transfer. Hardware registers are referred to by
their address. For example, R[0x3000] refers
to the register located at address 0x3000.
Driver variables can be accessed via two
hardware registers, R[0x338C] and R[0x3390].
To access a variable, its address first needs to
be written to R[0x338C], which is a standard
two-wire register write. Then, reading register
R[0x3390] reads the variable and writes a
value to it, thus setting the variable to that
value. Driver variables are referred to by their
address. For example, V[0x2797] refers to the
driver variable located at address 0x2797.
Configuration
The cameras start up with their registers set to
default values. This also means they are in
standby. To acquire images from the cameras,
both have to be initialized properly. As the
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VmodCAM Reference Manual
Enable output:
1. R[0x301A] = 0x02CC; parallel enable,
drive pins, start streaming.
preconfigured for preview mode. Context B is
for snapshot and video capture.
You can set the parameters using the two-wire
interface to command the sequencer to switch
contexts. If the parameters being modified
belong to the active mode, the changes only
take effect after the Refresh and Refresh Mode
commands are executed.
Sequencer
The sequencer is a state machine responsible
for coordinating events triggered by the user.
You can query the current state and instruct
the sequencer to change state.
The sequencer command variable V[0xA103]
accepts the following values:
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0-Run
1-Go to Preview
2-Go to Capture
3-Go to Standby
4-Do lock
5-Refresh
6-Refresh mode
Image Processing
Raw sensor data coming from the pixel array is
fed to a color processing pipeline called an
image flow processor (IFP). This is where all
the image processing, correction, scaling,
interpolation, and output formatting algorithms
are applied.
The IFP can also be bypassed, causing the
camera to output the uncompressed raw 10-bit
Bayer data in this mode.
The IFP is controlled indirectly, through
microprocessor variables and the sequencer.
The IFP can be controlled directly by
accessing its hardware registers, but normally
the on-chip microprocessor regularly adjusts
these parameters.
Output Formats
Mode
RGB565
RGB555
RGB444x
RGBx444
YUV
Byte
Odd
Even
Odd
Even
Odd
Even
Odd
Even
4*i
4*i+1
4*i+2
4*i+3
D7:D0
R
7
R
6
R
5
R
4
R
3
G
7
G
6
G
5
G
4
G
3
G
2
B
7
B
6
B
5
B
4
B
3
0R
7
R
6
R
5
R
4
R
3
G
7
G
6
G
5
G
4
G
3
B
7
B
6
B
5
B
4
B
3
R
7
R
6
R
5
R
4
G
7
G
6
G
5
G
4
B
7
B
6
B
5
B
4
0000
0000R
7
R
6
R
5
R
4
G
7
G
6
G
5
G
4
B
7
B
6
B
5
B
4
Cb
Y
Cr
Y
For the video capture, the Video bit (bit 1)
needs to set in variable V[0xA120]. Otherwise,
the capture state will only take a single
snapshot.
The sequencer state variable V[0xA104] reads:
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0-Initialize
1-Mode Change to Preview
2-Enter Preview
3-Preview
4-Leave Preview
5-Mode Change to Capture
6-Enter Capture
7-Capture
8-Leave Capture
9-Standby
Contexts
The microprocessor uses two contexts, each
with their own set of parameters. Context A is
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VmodCAM Reference Manual
Variable Address
Description
Current Context (0 = A, 1 = B)
Output Width
Output Height
Sensor Row Start
Sensor Row End
Sensor Column Start
Sensor Column End
Read Mode
Context A
Context B
Bits
7:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
11
10
7:5
4:2
1
0
15:0
15:0
15:0
15:0
15:0
8
0xA702
0x2703
0x2707
0x2705
0x2709
0x270D
0x272F
0x2711
0x2733
0x270F
0x2731
0x2713
0x2735
0x2719
0x273B
x-bin enable
xy-bin enable
x odd increment
y odd increment
vertical flip
(0=normal)
horizontal flip
(0=normal)
Crop X0
0x2751
0x275F
Crop X1
0x2753
0x2761
Crop Y0
0x2755
0x2763
Crop Y1
0x2757
0x2765
Output format
0x2795
0x2797
processed Bayer mode
RGB output format
0x0=RGB565
0x1=RGB555
0x2=RGB444x
0x3=RGBx444
RGB/YUV
0x1=RGB
0x0 = YUV
Use CCIR656 codes when bypassing FIFO
Monochrome output
Progressive Bayer
Swap chrominance/luminance bytes in YUV, swap odd/even bytes in
RGB
Swap Cr/Cb in YUV, swap R/B in RGB
Table 2
Image Parameters
Default
Context
Context
A
B
0x0000
800
1600
600
1200
0
4
1213
1211
0
4
1613
1611
0x046C
0x0024
0x0
0x0
0x1
0x0
0x3
0x1
0x3
0x1
0x0
0x0
0
800
0
600
0x0000
0x0
0x0
0x0
0
1600
0
1200
0x0000
0x0
7:6
0x0
0x0
5
4
3
2
1
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
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