For Communications Equipment
MN6152U
PLL LSI with Built-In Prescaler
Overview
The MN6152U is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.8 to 2.5 V) and low power consumption (5 mW
for V
DD
=2.0 V, F
IN
=100 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Pin Assignment
X
IN
X
OUT
FV
V
DD
D
OP
V
SS
LD
F
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OR
OV
LC
FR
PS
LE
DATA
CLK
Features
Low power supply voltage: V
DD
=1.8 to 2.5V
Low power consumption: 5mW (V
DD
=2.0V,
F
IN
=100MHz)
High-speed operation:
F
IN
=175MHz
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage: 272 to
262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and refer-
ence frequency dividing stages
(TOP VIEW)
SSOP016-P-0225
MN6152U
Block Diagram
Amplifier
Phase
matching
17-bit programmable counter
13
FR
X
IN
1
X
OUT
17-bit latch
2
CLK
9
Control
14
LC
DATA
18-bit shift register
10
Data control
7
LD
15
OV
16
OR
5
D
OP
Phase comparator
LE
18-bit latch
11
PS
12
3
Amplifier
Prescaler and
phase matching
Swallow
counter
For Communications Equipment
F
IN
8
14-bit programmable
counter
FV
For Communications Equipment
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
X
IN
X
OUT
FV
V
DD
D
OP
V
SS
LD
F
IN
CLK
Function Description
Crystal oscillator connection pins:
X
IN
=Oscillator circuit input pin;
X
OUT
=Oscillator circuit output pin.
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
Power supply
Low-pass filter connection pin. Use a passive filter.
Ground
Phase comparator output pin:
"H" level for locked; "L"level for unlocked.
Frequency divider input pin in comparating stage.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
10
DATA
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
11
LE
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
MN6152U
"H" level input starts the frequency divider and places the chip in operational mode.
12
PS
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13
FR
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
14
15
16
LC
OV
OR
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
Phase comparator output pin for external charge pump.
MN6152U
MN6152 Frequency Dividing Data Settings
For Communications Equipment
The following formula shows frequency divider operation.
F
IN
={ (16
×
N) + A}
×
(X
IN
÷ R)
where
F
IN
: VCO output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
X
IN
: Reference oscillator frequency
R
: Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB
14 bits
Programmable counter setting (N)
4 bits
LSB
Swallow counter setting (A)
For Communications Equipment
Absolute Maximum Ratings
Parameter
Power supply voltage
Input pin voltage
Output pin voltage
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
V
DD
V
I
V
O
P
D
T
opr
T
stg
Rating
– 0.3 to +3.5
V
SS
– 0.3 to V
DD
+0.3
V
SS
– 0.3 to V
DD
+0.3
20
–20 to +60
–55 to +125
MN6152U
Unit
V
mW
˚C
Operating Conditions
V
SS
=0V, Ta=–20
to
+60˚C
Parameter
Power supply voltage
Symbol
V
DD
Test Conditions
min
1.8
typ
2.0
max
2.5
Unit
V
Electric Characteristics
V
DD
=2V, Ta=–20
to
+60˚C
Parameter
Power supply voltage
Symbol
I
DD
I
Dstop
Test Conditions
F
IN
=100MHz, X
IN
=20MHz,
PS="H"
PS ="L" (at power save operation)
V
DD
=1.8
to
2.5V
min
typ
max
2.5
10
Unit
mA
µA
Input Pins
CLK, DATA, LE, and PS
V
IH
V
IL
I
LI
V
DD
=1.8
to
2.5V
"H" level input voltage
"L" level input voltage
Input leakage current
Input Pin
Input voltage
Input current
Input leakage current
Maximum operating frequency
Minimum operating frequency
Input Pin
Input voltage
Input current
Input leakage current
Maximum operating frequency
X
IN
F
IN
V
DD
– 0.2
V
SS
V
DD
0.2
±1.0
V
µA
V
p-p
µA
V
IN
I
IF
I
LIF
F
INMAX
F
INMIN
V
IN
I
IX
V
LIX
X
INMAX
Pull-up resistor present
(PS="L")
V
IN
=0 or 2V
V
IN
=0.4 V
p-p
Pull-up resistor present
(PS="L")
V
IN
=0 or 2V (PS="H")
V
IN
=0.4 V
p-p
V
IN
=0.4 V
p-p
0.4
–100
±20
175
10
0.4
2.5
5.0
20
µA
MHz
MHz
V
p-p
mA
µA
MHz
V
DD
=1.8
to
2.5V
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