Data Sheet No. PD60265
IRS2183/IRS21834(S)PbF
Features
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V and 5 V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5 V offset
Lower di/dt gate driver for better noise immunity
Output source/sink current capability 1.4 A/1.8 A
RoHS compliant
HALF-BRIDGE DRIVER
Packages
8-Lead PDIP
IRS2183
14-Lead PDIP
IRS21834
Description
The IRS2183/IRS21834 are high voltage,
high speed power MOSFET and IGBT
drivers with dependent high-side and
Feature Comparison
Cross-
low-side referenced output channels.
Deadtime
ton/toff
Input
conduction
Ground Pins
Part
Proprietary HVIC and latch immune
logic
prevention
(ns)
(ns)
logic
CMOS technologies enable ruggedized
2181
COM
HIN/LIN
no
none
180/220
monolithic construction. The logic input
21814
V
SS
/COM
is compatible with standard CMOS or
2183
Internal 400
COM
HIN/LIN
yes
180/220
21834
Program 400-5000
V
SS/
COM
LSTTL output, down to 3.3 V logic. The
2184
Internal 400
COM
IN/SD
yes
680/270
output drivers feature a high pulse cur-
21844
Program 400-5000
V
SS
/COM
rent buffer stage designed for minimum
driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT
in the high-side configuration which operates up to 600 V.
8-Lead SOIC
IRS2183S
14-Lead SOIC
IRS21834S
Typical Connection
V
CC
up to 600 V
V
CC
HIN
LIN
V
B
HO
V
S
LO
up to 600 V
TO
LOAD
HIN
LIN
COM
IRS2183
HO
V
CC
HIN
LIN
V
CC
HIN
LIN
DT
V
B
V
S
IRS21834
TO
LOAD
(Refer to Lead Assignment for correct pin
V
SS
configuration) These diagrams show electrical
connections only. Please refer to our Application
Notes and DesignTips for proper circuit board layout.
R
DT
V
SS
COM
LO
www.irf.com
1
IRS2183/IRS21834(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
DT
V
IN
V
SS
dV
S
/dt
Definition
High-side floating absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Programmable deadtime pin voltage (IR21834 only)
Logic input voltage (HIN &
LIN
)
Logic ground (IR21834 only)
Allowable offset supply voltage transient
(8-lead PDIP)
(8-lead SOIC)
(14-lead PDIP)
(14-lead SOIC)
(8-lead PDIP)
(8-lead SOIC)
(14-lead PDIP)
(14-lead SOIC)
Min.
-0.3
V
B
- 20
V
S
- 0.3
-0.3
-0.3
V
SS
- 0.3
V
SS
- 0.3
V
CC
- 20
—
—
—
—
—
—
—
—
—
—
-50
—
Max.
620 (Note 1)
V
B
+ 0.3
V
B
+ 0.3
20 (Note 1)
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
1.6
1.0
125
200
75
120
150
150
300
Units
V
V/ns
P
D
Package power dissipation @ T
A
≤
+25 °C
W
Rth
JA
Thermal resistance, junction to ambient
°C/W
T
J
T
S
T
L
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
°C
Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V
S
and V
SS
offset rating are tested with all supplies biased at 15 V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
DT
V
SS
T
A
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage (HIN &
LIN
)
Programmable deadtime pin voltage (IR21834 only)
Logic ground (IR21834 only)
Ambient temperature
Min.
V
S
+ 10
Note 2
V
S
10
0
V
SS
V
SS
-5
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
V
CC
5
125
Units
V
°
C
Note 2: Logic operational for V
S
of -5 V to +600 V. Logic state held for V
S
of -5 V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
www.irf.com
2
IRS2183/IRS21834(S)PbF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, V
SS
= COM, C
L
= 1000 pF, T
A
= 25 °C, DT = V
SS
unless otherwise specified.
Symbol
ton
toff
MT
tr
tf
DT
MDT
Definition
Turn-on propagation delay
Turn-off propagation delay
Delay matching
Min.
—
—
—
—
—
280
4
—
—
Typ.
180
220
0
40
20
400
5
0
0
Max. Units Test Conditions
270
330
35
60
35
520
6
50
600
µs
ns
ns
V
S
= 0 V
R
DT
= 0
Ω
R
DT
= 200 kΩ
(IR21834)
R
DT
=0
Ω
R
DT
= 200kΩ
(IR21834)
VS = 0V
V
S
= 0V or 600V
|
ton - toff
|
Turn-on rise time
Turn-off fall time
Deadtime: LO turn-off to HO turn-on(DT
LO-HO) &
HO turn-off to LO turn-on (DT
HO-LO)
Deadtime matching =
|
DT
LO-HO
- DT
HO-LO
|
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, V
SS
= COM, DT= V
SS
and T
A
= 25 °C unless otherwise specified. The V
IL
, V
IH,
and I
IN
parameters are referenced to V
SS
/COM and are applicable to the respective input leads: HIN and LIN. The V
O
, I
O,
and
Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
O+
I
O-
Definition
Logic “1” input voltage for HIN & logic “0” for
LIN
Logic “0” input voltage for HIN & logic “1” for
LIN
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
CC
and V
BS
supply undervoltage positive going
threshold
V
CC
and V
BS
supply undervoltage negative going
threshold
Hysteresis
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.5
—
—
—
—
20
0.4
—
—
8.0
7.4
0.3
1.4
1.8
—
—
—
—
—
60
1.0
25
—
8.9
8.2
0.7
1.9
2.3
—
0.8
1.4
0.2
50
150
1.6
60
5.0
9.8
9.0
—
—
A
—
V
O
= 0 V,
PW
≤
10 µs
V
O
= 15 V,
PW
≤
10 µs
V
µA
µA
mA
V
IN
= 0 V or 5 V
HIN = 5 V,
LIN
= 0 V
HIN = 0 V,
LIN
= 5 V
V
CC
= 10 V to 20 V
V
I
O
= 0 A
I
O
= 20 mA
V
B
= V
S
= 600 V
www.irf.com
3
IRS2183/IRS21834(S)PbF
Functional Block Diagrams
VB
2183
HV
LEVEL
SHIFTER
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
HIN
VSS/COM
LEVEL
SHIFT
VS
PULSE
GENERATOR
DT
DEADTIME &
SHOOT-THROUGH
PREVENTION
UV
DETECT
VCC
+5V
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
VSS
VB
21834
HIN
VSS/COM
LEVEL
SHIFT
HV
LEVEL
SHIFTER
PULSE
GENERATOR
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
VS
DT
+5V
DEADTIME &
SHOOT-THROUGH
PREVENTION
UV
DETECT
VCC
LO
LIN
VSS/COM
LEVEL
SHIFT
DELAY
COM
VSS
www.irf.com
4
IRS2183/IRS21834(S)PbF
Lead Definitions
Symbol Description
HIN
Logic input for high-side gate driver output (HO), in phase (referenced to COM for IRS2183
and VSS for IRS21834)
Logic input for low-side gate driver output (LO), out of phase (referenced to COM for IRS2183
and VSS for IRS21834)
Programmable deadtime lead, referenced to VSS (IRS21834 only)
Logic ground (IRS21834 only)
High-side floating supply
High-side gate driver output
High-side floating supply return
Low-side and logic fixed supply
Low-side gate driver output
Low-side return
LIN
DT
V
SS
V
B
HO
V
S
V
CC
LO
COM
Lead Assignments
1
2
3
4
HIN
LIN
COM
LO
VB
HO
VS
VCC
8
7
6
5
1
2
3
4
HIN
LIN
COM
LO
VB
HO
VS
VCC
8
7
6
5
8-Lead PDIP
8-Lead SOIC
IRS2183PbF
1
2
3
4
5
6
7
HIN
LIN
VSS
DT
COM
LO
VCC
VB
HO
VS
IRS2183SPbF
1
4
13
12
11
10
9
8
1
2
3
4
5
6
7
HIN
LIN
VSS
DT
COM
LO
VCC
VB
HO
VS
1
4
13
12
11
10
9
8
14-Lead PDIP
14-Lead SOIC
IRS21834PbF
www.irf.com
IRS21834SPbF
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
