TOSHIBA
TENTATIVE
TMPR4955/56
TOSHIBA RISC PROCESSOR
TMPR4955/TMPR4956F
(64-bit RISC MICROPROCESSOR)
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The information contained herein is subject to change without notice.
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TOSHIBA is continually working to improve the quality and the reliability of its products.
Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of
the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure
of a TOSHIBA product could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA
Semiconductor Reliability Handbook
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties, which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
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1
20-Oct.-1999
TOSHIBA
TENTATIVE
TMPR4955/56
1.
GENERAL DESCRIPTION
The TMPR4955/56F is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is
a low-cost, low-power microprocessor developed for interactive consumer applications including
set-top terminals, LBP(Laser Beam Printer), and video games.
2.
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FEATURES
True 64-bit microprocessor, with TX49/H core.
Optimized 5-stage pipeline
System Address/Data bus
TMPR4955 : 32-bit System Address/Data bus
TMPR4956 : 32-bit or 64-bit System Address/Data bus
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Floating-Point Operation
Single or double-precision floating-point unit ( IEEE Standard 754 exceptions )
36-bit physical address space and 64-bit virtual address space.
On-chip
32-Kbyte Instruction Cache and 32-Kbyte Data Cache.
4-way set associative and Lock function support
Low power consumption
3.3 /2.5V Dual power supply (I/O:3.3V,Internal:2.5V)
Reduced power mode (Doze/Halt)
Instruction cache prefetching
Memory management unit
contains 48-double entry JTLB, 2-entry Instruction TLB, and 4-entry Data TLB
Software compatibility with all MIPS processors
MIPS I, II, and III Instruction Set Architecture (ISA)
EJTAG (Enhanced JTAG) debug support
Package :
TMPR4955 : 160-pin QFP
TMPR4956 : 208-pin QFP
Maximum operating frequency
Internal:167/200MHz
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2
20-Oct.-1999
TOSHIBA
TENTATIVE
TMPR4955/56
3.
3.1
SYSTEM CONFIGURATION
TMPR4955/56F BLOCK DIAGRAM
4.
Master
Clock
TMPR4955/56F
PLL
Integer Unit
TX49/H Core
System Control
Coprocessor (CP0)
CP0 Registers
CP1 Registers
Data
Path
Pipeline
Controller
Floating-Point
Coprocessor (CP1)
Interrupt
/Reset
Synchronizer
GPR
MMU w/ TLB
Data Path
JTAG
Interface
DSU
(EJTAG)
MAC
Exception Unit
32/64-bit
SysAD Bus
(R5000 class)
SysAD
Interface
32K Byte
4-way Set
Instruction
Cache
Cache
Controller
32K Byte
4-way Set Data
Cache
Write Buffer
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20-Oct.-1999
TOSHIBA
TENTATIVE
TMPR4955/56
3.2 BLOCK FUNCTION
q
TX49/H Core
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True 64-bit microprocessor
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32, 64-bit integer general purpose registers
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32, 32-bit floating point general purpose registers
Optimized 5-stage pipeline
Instruction Set
Upward compatible with MIPS I,MIPS II, MIPS III ISA
MAC(Multiply and Accumulate) instructions
PREF(Prefetch) instruction
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On-chip 32-Kbyte Instruction Cache and 32-Kbyte Data Cache
4-way set associative and Lock function support
Data Cache: Write-back and Write-through support
MMU
36-bit physical address space and 64-bit virtual address space
48-double-entry (even/odd) Joint TLB
2-entry Instruction TLB and 4-entry Data TLB
IEEE754 compatible single and double precision FPU
Debug Support Unit (DSU) with EJTAG support
Power management modes ( HALT/DOZE )
SysAD BUS I/F
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Bus protocol conversion
It converts TX4955/56 Internal GBus Read/Write request into outside SysAD Bus protocol.
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q
q
Sysnchronizer
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The external interrupt
It takes contents of interrupt register and bitwise OR of external interrupt signal (INT(5:0)).
q
Clock Generator
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Generates the internal operating clock of the TX4955/56 from external crystal oscillator.
q
Debug Support Unit (DSU)
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EJTAG function support
Consists of an Enhanced JTAG (EJTAG) Module and a Debug Support Unit (DSU). It can
be used to provide single-step execution and hardware break-points for debugging
processor systems. EJTAG utilizes JTAG interface and extends the ability to access the
inside register contents, host sytem peripherals, and system memory.
4
20-Oct.-1999
TOSHIBA
TENTATIVE
TMPR4955/56
4.
PIN DESCRIPTION
4.1 PIN OUT ( TX4955 160-pin QFP)
1 Vss
2 VccIO
3 JTDO
4 JTDI
5 JTCK
6 JTMS
7 VccIO
8 Vss
9 SysAD4
10 SysAD5
11 VccInt
12 Vss
13 SysAD6
14 VccIO
15 Vss
16 SysAD7
17 SysAD8
18 VccInt
19 Vss
20 SysAD9
21 VccIO
22 Vss
23 SysAD10
24 SysAD11
25 VccInt
26 Vss
27 SysAD12
28 VccIO
29 Vss
30 SysAD13
31 SysAD14
32 VccInt
33 Vss
34 SysAD15
35 VccIO
36 PCST3
37 PCST2
38 PCST1
39 PCST0
40 VccIO
41 Vss
42 TRST*
43 RdRdy*
44 WrRdy*
45 ValidIn*
46 ValidOut*
47 Release*
48 VccIO
49 PLLReset*
50 VccInt
51 TintDis
52 Vss
53 SysCmd0
54 SysCmd1
55 SysCmd2
56 SysCmd3
57 SysCmd4
58 SysCmd5
59 VccIO
60 Vss
61 SysCmd6
62 SysCmd7
63 SysCmd8
64 SysCmdP
65 VccInt
66 Vss
67 VccIO
68 HALT/DOZE
69 Int0*
70 Int1*
71 Int2*
72 Int3*
73 Int4*
74 Int5*
75 VccIO
76 Vss
77 TPC3
78 TPC2
79 TPC1
80 DCLK
81 VccInt
82 NMI*
83 ExtRqst*
84 Reset*
85 ColdReset*
86 VccIO
87 Endian
88 VccIO
89 Vss
90 SysAD16
91 VccInt
92 Vss
93 SysAD17
94 SysAD18
95 VccIO
96 Vss
97 SysAD19
98 VccInt
99 Vss
100 SysAD20
101 SysAD21
102 VccIO
103 Vss
104 SysAD22
105 VccInt
106 Vss
107 SysAD23
108 SysAD24
109 VccIO
110 Vss
111 SysAD25
112 VccInt
113 Vss
114 SysAD26
115 SysAD27
116 VccIO
117 VccIO
118 DivMode1
119 DivMode0
120 Vss
121 SysAD28
122 SysAD29
123 VccInt
124 Vss
125 SysAD30
126 VccIO
127 Vss
128 SysAD31
129 SysADC2
130 VccInt
131 Vss
132 SysADC3
133 VccIO
134 Vss
135 SysADC0
136 VccInt
137 Vss
138 SysADC1
139 SysAD0
140 VccIO
141 Vss
142 SysAD1
143 SysAD2
144 VccInt
145 Vss
146 SysAD3
147 PCST8
148 PCST7
149 PCST6
150 PCST5
151 PCST4
152 VccIO
153 Vss
154 VccIO
155 VssPLL
156 PLLCAP
157 VccPLL
158 Vss
159 MasterClock
160 VccIO
Note: “ * “ means the signal is the low-active.
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20-Oct.-1999
PCB设计
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