74HC540; 74HCT540
Octal buffer/line driver; 3-state; inverting
Rev. 4 — 1 March 2016
Product data sheet
1. General description
The 74HC540; 74HCT540 is an 8-bit inverting buffer/line driver with 3-state outputs. The
device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs
to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Inverting outputs
Complies with JEDEC standard no. 7A
Input levels:
For 74HC540: CMOS level
For 74HCT540: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC540D
74HCT540D
74HC540DB
74HCT540DB
40 C
to +125
C
SSOP20
40 C
to +125
C
Name
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT163-1
SOT339-1
Type number
Nexperia
74HC540; 74HCT540
Octal buffer/line driver; 3-state; inverting
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT540
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 1 March 2016
2 of 17
Nexperia
74HC540; 74HCT540
Octal buffer/line driver; 3-state; inverting
Fig 3.
Functional diagram
74HC_HCT540
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 1 March 2016
3 of 17
Nexperia
74HC540; 74HCT540
Octal buffer/line driver; 3-state; inverting
Fig 4.
Logic diagram
74HC_HCT540
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 1 March 2016
4 of 17
Nexperia
74HC540; 74HCT540
Octal buffer/line driver; 3-state; inverting
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO20 and SSOP20
5.2 Pin description
Table 2.
Symbol
OE1
A0 to A7
GND
Y0 to Y7
OE2
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
output enable input (active LOW)
data input
ground (0 V)
data output
output enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Control
OE1
L
L
X
H
[1]
Functional table
[1]
Input
OE2
L
L
H
X
An
L
H
X
X
Output
Yn
H
L
Z
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74HC_HCT540
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 1 March 2016
5 of 17
嵌入式系统
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