74ABT657
Octal transceiver with parity generator/checker; 3-state
Rev. 03 — 15 March 2010
Product data sheet
1. General description
The 74ABT657 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs
and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The
buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input
(pin T/R) determines the direction of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW)
enables data from B ports to A ports.
When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The
parity select input (pin ODD/EVEN) allows the user to generate either an odd or even
parity output, depending on the system. Pin PARITY is an output from the
generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input
when receiving from port B to port A port (pin T/R = LOW).
In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH
inputs on port A. Pin PARITY output goes to the logic state determined by the setting of
pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin
ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin
PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port
A is even, pin PARITY output goes LOW, keeping even parity.
In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs
on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port
B is:
•
Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error
•
Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error
2. Features and benefits
I
I
I
I
I
I
Combinational functions in one package
Low static and dynamic power dissipation with high speed and high output drive
Output capability: +64 mA and
−32
mA
Power-up 3-state
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
N
HBM JESD22-A114F exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74ABT657D
74ABT657DB
−40 °C
to +85
°C
−40 °C
to +85
°C
Name
SO24
SSOP24
Description
plastic shrink small outline package; 24 leads; body width
5.3 mm
Version
SOT340-1
SOT355-1
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
Type number
74ABT657PW
−40 °C
to +85
°C
TSSOP24 plastic thin shrink small outline package; 24 leads; body
width 4.4 mm
4. Functional diagram
2
A0
1
24
11
T/R
OE
ODD/EVEN
B0 B1 B2
23
22
21
ERROR
B3
20
B4
17
B5
16
B6
15
B7
14
001aae826
3
A1
4
A2
5
A3
6
A4
8
A5
9
A6
10
A7
13
12
PARITY
Fig 1.
Logic symbol
1
24
11
0
1
M
0 0 BUS B TO A
1 BUS A TO B
2
2 HIGH Z
G3[EVEN]
G4[ODD]
2K
=
1,3[EVEN]
1,4[ODD]
0,3[EVEN
0,4]ODD
2
13
12
23
22
21
20
17
16
15
14
001aae827
2
3
4
5
6
8
9
10
0
Fig 2.
IEC logic symbol
74ABT657_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
2 of 17
NXP Semiconductors
74ABT657
Octal transceiver with parity generator/checker; 3-state
5. Pinning information
5.1 Pinning
74ABT657
T/R
A0
A1
A2
A3
A4
V
CC
A5
A6
1
2
3
4
5
6
7
8
9
24 OE
23 B0
22 B1
21 B2
20 B3
19 GND
18 GND
17 B4
16 B5
15 B6
14 B7
13 PARITY
001aae825
A7 10
ODD/EVEN 11
ERROR 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
T/R
A0 to A7
V
CC
ODD/EVEN
ERROR
PARITY
B0 to B7
GND
OE
Pin description
Pin
1
2, 3, 4, 5, 6, 8, 9, 10
7
11
12
13
23, 22, 21, 20, 17, 16, 15, 14
18, 19
24
Description
transmit/receive input
A port input/3-state output
positive supply voltage
parity select input
error output in receive mode
parity output in transmit mode/input in
receive mode
B port input/3-state output
ground (0 V)
output enable input (active LOW)
74ABT657_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
4 of 17
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