Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> A40MX04-1PQ100I

A40MX04-1PQ100I: 产品描述FPGA - Field Programmable Gate Array MX; 产品类别可编程逻辑器件可编程逻辑; 文件大小7MB，共142页; 制造商Microsemi; 官网地址https://www.microsemi.com

下载文档详细参数全文预览

A40MX04-1PQ100I在线购买

供应商	器件名称	价格	最低购买	库存
	A40MX04-1PQ100I	-	-	点击查看	点击购买

A40MX04-1PQ100I概述

FPGA - Field Programmable Gate Array MX

A40MX04-1PQ100I规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Microsemi
零件包装代码	QFP
包装说明	PLASTIC, QFP-100
针数	100
Reach Compliance Code	unknown
其他特性	ALSO OPERATES AT 5V SUPPLY
最大时钟频率	48 MHz
CLB-Max的组合延迟	2.3 ns
JESD-30 代码	R-PQFP-G100
JESD-609代码	e0
长度	20 mm
湿度敏感等级	3
可配置逻辑块数量	547
等效关口数量	6000
端子数量	100
最高工作温度	85 °C
最低工作温度	-40 °C
组织	547 CLBS, 6000 GATES
封装主体材料	PLASTIC/EPOXY
封装代码	QFP
封装形状	RECTANGULAR
封装形式	FLATPACK
峰值回流温度（摄氏度）	225
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
认证状态	Not Qualified
座面最大高度	3.4 mm
最大供电电压	3.6 V
最小供电电压	3 V
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	14 mm

文档预览

下载PDF文档

全文
预览

Revision 11

40MX and 42MX FPGA Families

Features

High Capacity

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

•

HiRel Features

•

Commercial, Industrial, Automotive,

Temperature Plastic Packages

and

Military

Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

QML Certification

Ceramic Devices Available to DSCC SMD

Mixed-Voltage Operation (5.0V or 3.3V for core and

I/Os), with PCI-Compliant I/Os

Up to 100% Resource Utilization and 100% Pin Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Ease of Integration

High Performance

Product Profile

Device

Capacity

System Gates

SRAM Bits

Logic Modules

Sequential

Combinatorial

Decode

Clock-to-Out

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

User I/O (maximum)

PCI

Boundary Scan Test (BST)

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

A40MX02

3,000

–

295

–

9.5 ns

–

147

–

44, 68

100

–

A40MX04

6,000

–

547

–

9.5 ns

–

273

–

44, 68, 84

100

–

A42MX09

14,000

–

348

336

–

5.6 ns

–

348

516

104

–

100, 160

100

176

–

A42MX16

24,000

–

624

608

–

6.1 ns

–

624

928

140

–

100, 160, 208

100

176

–

A42MX24

36,000

–

954

912

6.1 ns

–

954

1,410

176

Yes

160, 208

–

176

–

A42MX36

54,000

2,560

1,230

1,184

6.3 ns

1,230

1,822

202

Yes

–

208, 240

–

208, 256

272

May 2012

40MX and 42MX FPGA Families

Table of Contents

40MX and 42MX FPGA Families

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-83

Package Pin Assignments

PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

R ev i si o n 1 1

1 – 40MX and 42MX FPGA Families

General Description

Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are

single-chip solutions and provide high performance while shortening the system design and development

cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and

FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus

interfaces, DSP, and co-processor functions.

The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a

0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX

devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby power

consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a wide

variety of packages and speed grades.

A42MX24 and A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems,

enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a low-

power mode. The devices are fully compliant with the PCI Local Bus Specification (version 2.1). They

deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.

The 42MX24 and 42MX36 devices include system-level features such as IEEE Standard 1149.1 (JTAG)

Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port

SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can

efficiently address applications requiring wide datapath manipulation and can perform transformation

functions such as those required for telecommunications, networking, and DSP.

All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest

member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened

to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and

PQ208 devices are pin-compatible.

MX Architectural Overview

The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All

devices within these families are composed of logic modules, I/O modules, routing resources and clock

networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains

embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as

FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide-decode modules.

Logic Modules

The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of

logic functions with efficient use of interconnect routing resources (Figure

1-1 on page 1-2).

The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of

two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity

functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the

array; latches and flip-flops can be constructed from logic modules whenever required in the

application.

R ev i si o n 1 1

1 -1

A40MX04-1PQ100I

A40MX04-1PQ100I在线购买

A40MX04-1PQ100I概述

A40MX04-1PQ100I规格参数

文档预览

推荐资源