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INTEGRATED CIRCUITS
74ALVCH16841
20-bit bus interface D-type latch (3-State)
Product specification
IC24 Data Handbook
1998 Jul 27
Philips
Semiconductors
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
Wide supply voltage range of 1.2V to 3.6V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
V
CC
2Q6
2Q7
GND
2Q8
2Q9
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V
CC
2D6
2D7
GND
2D8
2D9
2LE
•
Current drive
±24
mA at 3.0 V
•
All inputs have bus hold circuitry
•
Output drive capability 50Ω transmission lines @ 85°C
•
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16841 has two 10-bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE)
control gates.
When nOE is LOW, the data in the registers appears at the outputs.
When nOE is High the outputs are in High-impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16841 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
SA00076
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5ns
PARAMETER
SYMBOL
Propagation delay
t
PHL
/t
PLH
nD
n
to nQ
n
Propagation delay
t
PHL
/t
PLH
nLE to nQ
n
C
I
Input capacitance
C
PD
Power dissipation capacitance per buffer
dissi ation ca acitance er
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
V
I
= GND to V
CC1
Outputs enabled
Outputs disabled
TYPICAL
2.5
2.4
2.5
2.4
5.0
19
3
UNIT
ns
ns
pF
pF
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16841 DGG
NORTH AMERICA
ACH16841 DGG
DWG NUMBER
SOT364-1
1998 Jul 27
2
853-2093 19785
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
PIN DESCRIPTION
PIN NUMBER
1
56
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
2, 3, 5, 6, 8, 9, 10,
12, 13, 14
4, 11, 18, 25, 32,
39, 46, 53
7, 22, 35, 50
28
29
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
SYMBOL
1OE
1LE
1D0 – 1D9
1Q0 – 1Q9
GND
V
CC
2OE
2LE
2D0 – 2D9
2Q0 – 2Q9
FUNCTION
Output enable inputs
(active-LOW)
Latch enable inputs
(active HIGH)
Data inputs
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1D0
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
3D
4
∇
EN2
C1
EN4
C3
1D
2
∇
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
Data outputs
Ground (0V)
Positive supply
voltage
Output enable inputs
(active-LOW)
Latch enable inputs
(active HIGH)
Data inputs
Data outputs
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
FUNCTION TABLE
INPUTS
nOE
L
L
L
H
L
X
Z
=
=
=
=
LE
H
H
L
Dx
L
H
X
OUTPUT
Q
L
H
Q
0
Z
2D4
2D5
2D6
2D7
2D8
2D9
SH00152
H
X
X
High voltage level
Low voltage level
Don’t care
High impedance “off” state
LOGIC DIAGRAM
nD
0
LOGIC SYMBOL
55
54
52
51
49
48
47
45
44
43
D
1D0 1D1 1D2 1D3 1D4 1D5 1D6
56
1
1LE
1OE
1D7 1D8
1D9
LE
nLE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
nOE
2
42
3
41
5
40
6
38
8
37
9
36
10
34
12
33
13
31
14
nQ
0
30
SH00151
2D0 2D1 2D2 2D3 2D4 2D5 2D6
29
28
2LE
2OE
2D7 2D8
2D9
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
1998 Jul 27
3
Philips Semiconductors
Product specification
20-bit bus interface D-type latch (3-State)
74ALVCH16841
BUS HOLD CIRCUIT
V
CC
Data Input
To internal circuit
SW00044
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
CONDITIONS
MIN
2.3
3.0
0
0
–40
0
0
MAX
2.7
V
3.6
V
CC
V
CC
+85
20
10
V
V
°C
ns/V
UNIT
V
I
V
O
T
amb
t
r
, t
f
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC in ut voltage
input
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic medium-shrink (SSOP)
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
1
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
850
600
V
mA
V
mA
mA
°C
mW
UNIT
V
mA
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 27
4
FPGA/CPLD
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