DATASHEET
HD-6402
CMOS Universal AsynchronousReceiver Transmitter (UART)
The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when
transmitting 5-bit code.
The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements, by
comparison, are reduced from 300mW to 10mW. Status
logic increases flexibility and simplifies the user interface.
FN2956
Rev 4.00
August 25, 2015
Features
• 8.0MHz Operating Frequency (5962-9052502)
• 2.0MHz Operating Frequency (HD3-6402R)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
HD-6402 (PDIP, CERDIP)
TOP VIEW
V
CC
NC
GND
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFD
RRC
DRR
DR
RRI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 TRC
39 EPE
38 CLS1
37 CLS2
36 SBS
35 PI
34 CRL
33 TBR8
32 TBR7
31 TBR6
30 TBR5
29 TBR4
28 TBR3
27 TBR2
26 TBR1
25 TRO
24 TRE
23 TBRL
22 TBRE
21 MR
FN2956 Rev 4.00
August 25, 2015
Page 1 of 9
HD-6402
Ordering Information
PART NUMBER
(Note)
HD3-6402R-9
(No longer
available or supported)
HD3-6402R-9Z
(No longer
available or supported)
SMD 5962-9052502MQA
TEMP.
RANGE (°C)
-40 to +85
40 to +85
-55 to +125
2MHz
125k BAUD
125k BAUD
500k BAUD
8MHz
PACKAGE
40 Ld PDIP
40 Ld PDIP*
40 Ld CERDIP
PKG DWG. #
E40.6
E40.6
F40.6
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
FN2956 Rev 4.00
August 25, 2015
Page 2 of 9
HD-6402
Functional Diagram
TBR8
(24) TRE
(22) TBRE
†
(23) TBRL
(40) TRC
TRANSMITTER
TIMING AND
CONTROL
STOP
PARITY
LOGIC
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
TBR1
TRANSMITTER BUFFER REGISTER
TRANSMITTER REGISTER
MULTIPLEXER
(25) TRO
START
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
CONTROL
REGISTER
(36) SBS
(16) SFD
(39) EPE
(35) PI
(20) RRI
(17) RRC
(18) DRR
(19) DR
†
RECEIVER
TIMING AND
CONTROL
STOP
LOGIC
PARITY
LOGIC
MULTIPLEXER
RECEIVER REGISTER
RECEIVER BUFFER REGISTER
START
LOGIC
(16) SFD
†
THESE OUTPUTS ARE
THREE-STATE
3-STATE
BUFFERS
†
RBR8
†
OE
(15)
†
FE
(14)
†
PE
(13)
†
RBR1
(5) (6) (7) (8) (9) (10) (11) (12)
(4) RRD
Control Definition
CONTROL WORD
CLS 2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
CLS 1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
PI
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
EPE
0
0
1
1
X
X
0
0
1
1
X
x
0
0
1
1
X
x
0
0
1
1
X
x
SBS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
START BIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CHARACTER FORMAT
DATA BITS
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
PARITY BIT
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
STOP BITS
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
FN2956 Rev 4.00
August 25, 2015
Page 3 of 9
HD-6402
Pin Description
PIN TYPE SYMBOL
1
2
3
4
I
V
CC
†
NC
GND
RRD
No Connection
Ground
A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.
The contents of the RECEIVER BUFFER REGIS-
TER appear on these three-state outputs. Word for-
mats less than 8 characters are right justified to
RBR1.
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
A high level on PARITY ERROR indicates received
parity does not match parity programmed by control
bits. When parity is inhibited this output is low.
A high level on FRAMING ERROR indicates the
first stop bit was invalid.
A high level on OVERRUN ERROR indicates the
data received flag was not cleared before the last
character was transferred to the receiver buffer
register.
A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
The Receiver register clock is 16X the receiver
data rate.
A low level on DATA RECEIVED RESET clears
the data received output DR to a low level.
A high level on DATA RECEIVED indicates a
character has been received and transferred to
the receiver buffer register.
Serial data on RECEIVER REGISTER INPUT is
clocked into the receiver register.
A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiv-
er buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
V
IH
and t
MR
. Wait 18 clock cycles after the falling
edge of MR before beginning operation.
A high level on TRANSMITTER BUFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has transferred its data to the transmitter register
and is ready for new data.
A low level on TRANSMITTER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
high transition on TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
transmitted end to end.
25
26
O
I
TRO
TRB1
DESCRIPTION
Positive Voltage Supply
PIN TYPE SYMBOL
24
O
TRE
DESCRIPTION
A high level on TRANSMITTER REGISTER EMP-
TY indicates completed transmission of a charac-
ter including stop bits.
Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
Character data is loaded into the TRANSMITTER
BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro-
grammed word length.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
These inputs program the CHARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)
See Pin 37-CLS2.
When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A low
level selects odd parity.
The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
5
O
RBR8
6
7
8
9
10
11
12
13
O
O
O
O
O
O
O
O
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
27
28
29
30
31
32
33
34
I
I
I
I
I
I
I
I
TBR2
TBR3
TBR4
TBR5
TBR6
TBR7
TBR8
CRL
14
15
O
O
FE
OE
35
36
I
I
PI
SBS
16
I
SFD
37
I
CLS2
17
18
19
I
I
O
RRC
DRR
DR
38
39
I
I
CLS1
EPE
40
I
TRC
20
21
I
I
RRI
MR
†
A 0.1F decoupling capacitor from the V
CC
pin to the GND is
recommended.
22
O
TBRE
23
I
TBRL
FN2956 Rev 4.00
August 25, 2015
Page 4 of 9
HD-6402
20
21
19
22
18
23
17
24
16
25
15
26
14
27
13
28
12
29
HD-6402
11
30
10
31
9
32
8
33
7
34
6
35
5
36
4
37
3
38
2
39
1
40
Transmitter Operation
The transmitter section accepts parallel data, formats the data
and transmits the data in serial form on the Transmitter
Register Output (TRO) terminal (See serial data format). Data
is loaded from the inputs TBR1-TBR8 into the Transmitter
Buffer Register by applying a logic low on the Transmitter
Buffer Register Load (TBRL) input (A). Valid data must be
present at least t
set
prior to and t
hold
following the rising edge
of TBRL. If words less than 8 bits are used, only the least
significant bits are transmitted. The character is right justified,
so the least significant bit corresponds to TBR1 (B).
The rising edge of TBRL clears Transmitter Buffer Register
Empty (TBRE). 0 to 1 Clock cycles later, data is transferred
to the transmitter register, the Transmitter Register Empty
(TRE) pin goes to a low state, TBRE is set high and serial
data information is transmitted. The output data is clocked by
Transmitter Register Clock (TRC) at a clock rate 16 times
the data rate. A second low level pulse on TBRL loads data
into the Transmitter Buffer Register (C). Data transfer to the
transmitter register is delayed until transmission of the cur-
rent data is complete (D). Data is automatically transferred to
the transmitter register and transmission of that character
begins one clock cycle later.
1
TBRL
TBRE
0 TO 1 CLOCK
TRE
TRO
A
B
C
DATA
D
END OF LAST STOP BIT
1/2 CLOCK
FIGURE 1. TRANSMITTER TIMING (NOT TO SCALE)
Receiver Operation
Data is received in serial form at the Receiver Register Input
(RRI). When no data is being received, RRI must remain
high. The data is clocked through the Receiver Register
Clock (RRC). The clock rate is 16 times the data rate. A low
level on Data Received Reset (DRR) clears the Data
Receiver (DR) line (A). During the first stop bit data is
transferred from the Receiver Register to the Receiver
Buffer Register (RBR) (B). If the word is less than 8 bits, the
unused most significant bits will be a logic low. The output
character is right justified to the least significant bit RBR1. A
logic high on Overrun Error (OE) indicates overruns. An
overrun occurs when DR has not been cleared before the
present character was transferred to the RBR. One clock
cycle later DR is reset to a logic high, and Framing Error
(FE) is evaluated (C). A logic high on FE indicates an invalid
stop bit was received, a framing error. A logic high on Parity
Error (PE) indicates a parity error.
FN2956 Rev 4.00
August 25, 2015
Page 5 of 9
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
