AN-225: 12-Bit Voltage-Output DACs for Single-Supply 5V
and 12V Systems
Data Sheet
•
AD7243: LC
2
MOS 12-Bit Serial DACPORT Data Sheet
•
AD7243: Military Data Sheet
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REFERENCE MATERIALS
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AD7243–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
3
Differential Nonlinearity
3
Unipolar Offset Error
3
Bipolar Zero Error
3
Full-Scale Error
3, 4
Full-Scale Temperature Coefficient
5
REFERENCE OUTPUT
Reference Output Range, REFOUT
Reference Temperature Coefficient
5
Reference Load Change
(∆REFOUT
VS
. I
L
)
REFERENCE INPUT
Reference Input Range, REFIN
Input Current
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance
5
DIGITAL OUTPUT
Serial Data Out (SDO)
Output Low Voltage, V
OL
Output High Voltage, V
OH
ANALOG OUTPUT
Output Range Resistor, R
OFS
Output Voltage Ranges
6
Output Voltage Ranges
6
DC Output Impedance
5
AC CHARACTERISTICS
5
Voltage Output Settling-Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse
3
Digital Feedthrough
3
POWER REQUIREMENTS
V
DD
Range
V
SS
Range (Dual Supplies)
I
DD
I
SS
(Dual Supplies)
A
2
12
±
1
±
0.9
±
4
±
5
±
6
±
5
B
2
12
±
1/2
±
0.9
±
4
±
5
±
6
±
5
(V
DD
= +12 V to +15 V,
1
V
SS
= 0 V or –12 V to –15 V,
1
AGND = DGND = O V, REFIN = +5 V,
R
L
= 2 k , C
L
= 100 pF to AGND. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
S
2
12
±
1
±
0.9
±
5
±
6
±
7
±
5
Unit
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
ppm of FSR/
°C
typ
V min/V max
ppm/°C typ
mV max
V min/V max
µA
max
V min
V max
µA
max
pF max
Test Conditions/Comments
Guaranteed Monotonic
V
SS
= 0 V or –12 V to –15 V
1
; DAC Latch
Contents All 0s
V
SS
= –12 V to –15 V
1
; DAC Latch Contents All 0s
Guaranteed By Process
4.95/5.05
±
25
–1
4.95/5.05
5
2.4
0.8
±
1
8
4.95/5.05
±
25
–1
4.95/5.05
5
2.4
0.8
±
1
8
4.95/5.05
±
30
–1
4.95/5.05
5
2.4
0.8
±
1
8
Guaranteed By Process
Reference Load Current (I
L
) Change (0–100
µA)
5 V
±
1% for Specified Performance
V
IN
= 0 V to V
DD
0.4
4.0
15/30
+5, +10
+5, +10,
±5
0.5
0.4
4.0
15/30
+5, +10
+5, +10,
±
5
0.5
0.4
4.0
15/30
+5, +10
+5, +10,
±
5
0.5
V max
V min
kΩ min/max
V
V
Ω
typ
I
SINK
= 1.6 mA
I
SOURCE
= 400
µA
Typically 20 k . Guaranteed By Process
Single Supply; V
SS
= 0 V
Dual Supply; V
SS
= –12 V to –15 V
10
10
30
10
+10.8/+16.5
–10.8/–16.5
10
2
10
10
30
10
+10.8/+16.5
–10.8/–16.5
10
2
10
10
30
10
+11.4/+15.75
–11.4/–15.75
10
2
µs
max
µs
max
nV secs typ
nV secs typ
V min/V max
V min/V max
mA max
mA max
Settling Time to Within
±
1/2 LSB of Final Value
Typically 4
µs
Typically 5
µs
DAC Latch Contents Toggled Between All 0s
and All 1s
LDAC
= High
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 7 mA
Output Unloaded; Typically 1 mA
NOTES
1
Power Supply Tolerance A, B Versions:
±
10%; S Version:
±
5%.
2
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
3
See terminology.
4
Measured with respect to REFIN and includes unipolar/bipolar offset error.
5
Guaranteed by design and characterization, not production tested.
6
0 V to +10 V output range is available only with V
DD
≥
+14.25 V.
Specifications subject to change without notice.
–2–
REV. A
AD7243
TIMING CHARACTERISTICS
Parameter
t
1 3
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
104, 5
t
114, 6
200
15
70
0
40
0
20
0
20
160
>t
5
1, 2
(V
DD
= +10.8 V to +16.5 V, V
SS
= 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,
R
L
= 2 k , C
L
= 100 pF. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
Conditions/Comments
SCLK Cycle Time
SYNC
to SCLK Falling Edge Setup Time
SYNC
to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC
High to
LDAC
Low
LDAC
Pulsewidth
LDAC
High to
SYNC
Low
CLR
Pulsewidth
SCLK Falling Edge to SDO Valid
SCLK Falling Edge to SDO Invalid
Limit at +25 C, T
MIN
, T
MAX
(All Versions)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 7 & 8.
3
SCLK mark/space ratio range is 40/60 to 60/40.
4
SDO load capacitance is no greater than 50 pF.
5
At 25°C t
10
is 130 ns max.
6
Guaranteed by design.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND, DGND . . . . . . . . . . . . . . . . . –0.3 V to +17 V
V
SS
to AGND, DGND . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
OUT2
to AGND . . . . . . . . . . . . . . . . . . . –6 V to V
DD
+ 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
DD
REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
SDO to DGND . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
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