HCF4040B
RIPPLE-CARRY BINARY COUNTER/DIVIDERS 12 STAGE
s
s
s
s
s
s
s
s
s
s
MEDIUM SPEED OPERATION :
t
PD
= 80ns (TYP.) at V
DD
= 10V
FULLY STATIC OPERATION
COMMON RESET
BUFFERED INPUTS AND OUTPUTS
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED UP TO
20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DIP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
DESCRIPTION
The HCF4040B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
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The HCF4040B is a ripple carry binary counter. All
counter stages are master-slave flip-flops. The
state of a counter advances one count on the
negative transition of each input pulse; a high level
on the RESET line resets the counter to its all
zeros stage. Schmitt trigger action on the input
pulse line permits unlimited clock rise and fall
times.
All inputs and outputs are buffered
so
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HCF4040BEY
HCF4040BM1
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T&R
HCF4040M013TR
PIN CONNECTION
September 2001
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HCF4040B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
I
I
I
P
D
T
op
T
stg
Supply Voltage
DC Input Voltage
DC Input Current
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
Storage Temperature
Parameter
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I
T
op
b
O
et
l
so
Supply Voltage
Input Voltage
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Unit
V
V
mA
mW
mW
°C
°C
Value
-0.5 to +22
-0.5 to V
DD
+ 0.5
±
10
200
100
-55 to +125
-65 to +150
Parameter
Value
3 to 20
0 to V
DD
-55 to 125
Unit
V
V
°C
Operating Temperature
3/10
HCF4040B
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25°C, C
L
= 50pF, R
L
= 200KΩ, t
r
= t
f
= 20 ns)
Test Condition
Symbol
Parameter
V
DD
(V)
INPUT-PULSE OPERATION
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
RESET OPERATION
5
10
15
5
10
15
5
10
15
Min.
Value (*)
Typ.
180
80
65
100
40
30
100
50
40
70
30
20
Max.
360
160
130
200
80
60
200
100
80
140
60
40
Unit
t
PLH
t
PHL
Propagation Delay Time
(∅ to Q1 Out)
t
PLH
t
PHL
Propagation Delay Time
(Qn to Qn+1)
t
THL
t
TLH
Transition Time
ns
ns
t
W
Minimum Input Pulse
Width
Input Pulse Rise and Fall
Time
Maximum Clock Input
Frequency
t
r
, t
f
f
max
t
PHL
Propagation Delay Time
t
W
Minimum Reset Pulse
Width
Reset Removal Time
t
REM
(*) Typical temperature coefficient for all V
DD
value is 0.3 %/°C.
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7
16
24
140
60
50
100
40
30
175
75
50
s)
t(
ns
ns
unlimited
µs
3.5
8
12
MHz
280
120
100
200
80
60
350
150
100
ns
ns
ns
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