Differential-to-LVDS Fanout Buffer w/Divider
and Glitchless Switch
ICS854S1208I
DATA SHEET
General Description
The
ICS854S1208I is a low skew, 8 output LVDS Fanout Buffer with
selectable divider. The ICS854S1208I has 2 selectable inputs that
accept a variety of differential input types. The device provides the
capability to suppress any glitch at the outputs of the device during
an input clock switch to enhance clock redundancy in fault tolerant
applications.
The divide select inputs, DIV_SELA and DIV_SELB, control the
output frequency of each bank. The output banks can be
independently selected for ÷1 or ÷2 operation. The output enable
pins assigned to each output, support enabling and disabling each
output individually.
The ICS854S1208I is characterized at full 3.3V or 2.5V output
operating supply modes. Guaranteed output and part-to-part skew
characteristics make the ICS854S1208I ideal for high performance
applications.
Features
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Eight differential LVDS output pairs
Each output has individual synchronous output enable
Two selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HCSL
Maximum output frequency: 1.5GHz
Independent bank control for ÷1 or ÷2 operation
Glitchless output behavior during input switch
Output skew: 40ps (maximum)
Bank skew: 35ps (maximum)
Full 3.3V or 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Supply Mode Operation Table
3.3V Operation
V
DD
= 3.3V
V
TAP
= Float
2.5V Operation
V
DD
= 2.5V
V
TAP
= 2.5V
V
DD
DIV_SELA
V
TAP
CLK0
nCLK0
GND
CLK_SEL
nCLK1
CLK1
GND
DIV_SELB
V
DD
Pin Assignment
GND
QA2
nQA2
QA3
nQA3
V
DD
V
DD
nQB3
QB3
nQB2
QB2
GND
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
nQA1
V
DD
V
DD
nQB1
QB1
nQB0
QB0
GND
GND
QA0
nQA0
QA1
V
DD
OEB0
OEB1
OEB2
OEB3
GND
V
DD
OEA3
OEA2
OEA1
OEA0
V
DD
ICS854S1208I
48-Pin TQFP, E-Pad
7mm x 7mm x 1mm package body
Y Package
Top View
ICS854S1208AYI REVISION A APRIL 27, 2012
1
©2012 Integrated Device Technology, Inc.
ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Block Diagram
V
TAP
QA0
DIV_SELA
Pulldown
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
nCLK1
Pullup/Pulldown
CLK_SEL
Pulldown
nQA0
Pullup
OEA0
QA1
0
÷1
0
nQA1
Pullup
OEA1
QA2
÷2
1
1
nQA2
Pullup
OEA2
QA3
nQA3
Pullup
OEA3
QB0
nQB0
Pullup
OEB0
QB1
0
nQB1
Pullup
OEB1
QB2
1
nQB2
Pullup
OEA2
QB3
nQB3
Pullup
OEB3
DIV_SELB
Pulldown
ICS854S1208AYI REVISION A APRIL 27, 2012
2
©2012 Integrated Device Technology, Inc.
ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Function Description
The ICS854S1208I has a glitch free input mux that is controlled by
the CLK_SEL pin. It is designed to switch between 2 input clocks
whether running or not. In the case where both clocks are running,
when CLK_SEL changes, the output clocks go low after one cycle
of the output clock (nominally). The outputs then stay low for one
cycle of the new input clock (nominally) and then begin to follow the
new input clock. This is shown in
Figure 1A.
CLK0
CLK1
CLK_SEL
Output
Figure 1A. CLK_SEL Timing Diagram
Another case is where one of the inputs was selected and running but
has since stopped (either high or low). If a CLK_SEL event happens
after a clock has stopped, the output change can take effect up to 1µs
after the input clock stopped. The output will go low and then follow
the second period of the new clock input. Figure 1B shows an
example of this.
CLK0
CLK1
CLK_SEL
Output
1µs
Figure 1B. CLK_SEL with Bad Input Timing Diagram
ICS854S1208AYI REVISION A APRIL 27, 2012
3
©2012 Integrated Device Technology, Inc.
ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Table 1. Pin Descriptions
Number
1, 12, 18, 19, 25,
30, 36, 42, 43
2
3
4
5
6, 10, 13, 24,
31, 37, 48
7
8
9
11
14, 15
16, 17
20, 21
22, 23
26
27
28
29
32
33
34
35
38, 39
40, 41
44, 45
46, 47
Name
V
DD
DIV_SELA
V
TAP
CLK0
nCLK0
GND
CLK_SEL
nCLK1
CLK1
DIV_SELB
QA0, nQA0
QA1, nQA1
nQB1, QB1
nQB0, QB0
OEA0
OEA1
OEA2
OEA3
OEB3
OEB2
OEB1
OEB0
QB2, nQB2
QB3, nQB3
nQA3, QA3
nQA2, QA2
Power
Input
Power
Input
Input
Power
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Power supply pins.
Controls frequency division for QA[0:3], nQA[0:3] outputs.
LVCMOS / LVTTL interface levels.
Power supply mode. See
Supply Mode Operation Table
on page 1.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Power supply ground.
Clock select input. When HIGH, selects CLK1/nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Controls frequency division for QB[0:3], nQB[0:3] outputs.
LVCMOS / LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output enable for QA0 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QA1 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QA2 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QA3 output pair. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable for QB3 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Output enable for QB2 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Output enable for QB1 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Output enable for QB0 output pair. LVCMOS/LVTTL interface levels.
See Table 3B.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
ICS854S1208AYI REVISION A APRIL 27, 2012
4
©2012 Integrated Device Technology, Inc.
ICS854S1208I Data Sheet
DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3A. OEAx Function Table
Inputs
OEA[0:3]
0
1 (default)
QA[0:3]
LOW
Active
Outputs
nQA[0:3]
HIGH
Active
Table 3B. OEBx Function Table
Inputs
OEB[0:3]
0
1 (default)
QB[0:3]
LOW
Active
Outputs
nQB[0:3]
HIGH
Active
Table 3C. DIV_SELA Function Table
Input
DIV_SELA
0 (default)
1
Frequency Division
÷1
÷2
Table 3D. DIV_SELB Function Table
Input
DIV_SELB
0 (default)
1
Frequency Division
÷1
÷2
Table 3E. CLK_SEL Function Table
Input
CLK_SEL
0 (default)
1
Input Selection
CLK0, nCLK0
CLK1, nCLK1
ICS854S1208AYI REVISION A APRIL 27, 2012
5
©2012 Integrated Device Technology, Inc.
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