CY62148EV30 MoBL
®
4-Mbit (512K × 8) Static RAM
4-Mbit (512K × 8) Static RAM
Features
■
Functional Description
The CY62148EV30 is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (I/O
0
through I/O
7
)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
For a complete list of related 1documentation,
click here.
Very high speed: 45 ns
❐
Wide voltage range: 2.20 V to 3.60 V
Temperature range:
❐
Industrial: –40 °C to +85 °C
❐
Automotive-A: –40 °C to +85 °C
Pin compatible with CY62148DV30
Ultra low standby power
❐
Typical standby current: 1
A
❐
Maximum standby current: 7
A
(Industrial)
Ultra low active power
❐
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 36-ball very fine-pitch ball grid array
(VFBGA), 32-pin thin small outline package (TSOP) II, and
32-pin small outline integrated circuit (SOIC)
[1]
packages
■
■
■
■
■
■
■
■
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CE
WE
OE
INPUT BUFFER
ROW DECODER
I/O
0
I/O
1
I/O
2
SENSE AMPS
IO0
IO1
IO2
IO3
512K x 8
ARRAY
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
IO4
IO5
IO6
COLUMN DECODER
POWER
DOWN
IO7
A13
A14
A15
A16
Note
1. SOIC package is available only in 55 ns speed bin.
A17
A18
Cypress Semiconductor Corporation
Document Number: 38-05576 Rev. *U
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 18, 2016
CY62148EV30 MoBL
®
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-05576 Rev. *U
Page 2 of 19
CY62148EV30 MoBL
®
Pin Configuration
VFBGA, SOIC and TSOP II pinouts are as follows.
[2, 3]
36-ball VFBGA pinout
Top View
NC
WE
NC
A
3
A
4
A
5
A
6
A
7
A
8
I/O
0
I/O
1
V
cc
V
ss
A
18
OE
A
10
CE
A
11
A
17
A
16
A
12
A
15
A
13
I/O
2
I/O
3
A
14
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
32-pin SOIC/TSOP II pinout
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
0
I/O
4
I/O
5
V
SS
V
CC
I/O
6
I/O
7
A
9
A
1
A
2
A
B
C
D
E
F
G
H
V
CC
A
15
A
18
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
Product Portfolio
Product
Range
V
CC
Range (V)
Min
CY62148EV30LL VFBGA
TSOP II
SOIC
Industrial
Industrial /
Automotive-A
Industrial
2.2
3.0
3.6
55
2
2.5
15
20
1
7
2.2
Typ
[4]
3.0
Max
3.6
45
Speed
(ns)
Power Dissipation
Operating I
CC
(mA)
f = 1 MHz
Typ
[4]
2
Max
2.5
f = f
max
Typ
[4]
15
Max
20
Standby I
SB2
(µA)
Typ
[4]
Max
1
7
Notes
2. SOIC package is available only in 55 ns speed bin.
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 38-05576 Rev. *U
Page 3 of 19
CY62148EV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ..................................... 55 °C to +125 °C
Supply voltage
to ground potential .......................–0.3 V to V
CC(max)
+ 0.3 V
DC voltage applied to outputs
in High Z State
[5, 6]
......................–0.3 V to V
CC(max)
+ 0.3 V
DC input voltage
[5, 6]
...................–0.3 V to V
CC(max)
+ 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Product
CY62148EV30
Range
Industrial /
Automotive-A
Ambient
V
CC
[7]
Temperature
–40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
Description
Test Conditions
-45 (Industrial /
Automotive-A)
Min Typ
Output high voltage I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70 V
Output low voltage
Input high voltage
Input low voltage
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70 V
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.2 V to 2.7 V For VFBGA and
TSOP II packages
For SOIC package
V
CC
= 2.7 V to 3.6 V For VFBGA and
TSOP II packages
For SOIC package
I
IX
I
OZ
I
CC
I
SB1 [11]
Input leakage
current
Output leakage
current
V
CC
operating
supply current
GND < V
I
< V
C
GND < V
O
< V
CC
, Output disabled
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max)
,
I
OUT
= 0 mA, CMOS
levels
2.0
2.4
–
–
1.8
2.2
–0.3
–
–0.3
–
–1
–1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15
2
1
[9]
-55
[8]
Min Typ
2.0
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15
2
1
[9]
Unit
Max
–
–
0.2
0.4
V
V
V
V
V
V
V
V
V
Max
–
–
0.4
0.4
V
CC
+ 0.3 1.8
V
CC
+ 0.3 2.2
0.6
–
0.8
–
+1
+1
20
2.5
7
–
–0.3
–
–0.3
–1
–1
–
–
–
V
CC
+ 0.3
V
CC
+ 0.3
–
0.4
[10]
–
0.6
[10]
+1
+1
20
2.5
7
A
A
mA
Automatic CE power CE > V
CC
– 0.2 V,
down current –
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V
CMOS inputs
f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60 V
A
I
SB2 [11]
Automatic CE power CE > V
CC
– 0.2 V,
down current –
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 3.60 V
CMOS inputs
–
1
7
–
1
7
A
Notes
5. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100
s
ramp time from 0 to V
CC(min)
and 200
s
wait time after V
CC
stabilization.
8. SOIC package is available only in 55 ns speed bin.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
10. Under DC conditions the device meets a V
IL
of 0.8V (for V
CC
range of 2.7 V to 3.6 V) and 0.6 V (for V
CC
range of 2.2 V to 2.7 V). However, in dynamic conditions
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only.
11. Chip Enable (CE) must be HIGH at CMOS level to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document Number: 38-05576 Rev. *U
Page 4 of 19
CY62148EV30 MoBL
®
Capacitance
Parameter
[12]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
[12]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
36-ball VFBGA 32-pin TSOP II
Package
Package
44.79
23.17
59.10
12.19
32-pin SOIC
Package
51.57
25.01
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
V
CC
OUTPUT
R1
ALL INPUT PULSES
V
CC
30 pF
R2
GND
Rise Time = 1 V/ns
10%
90%
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN
EQUIVALENT
OUTPUT
R
TH
V
TH
Parameters
R
1
R
2
R
TH
V
TH
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05576 Rev. *U
Page 5 of 19
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