XC61F
Series
Voltage Detectors, Delay Circuit Built-In
ETR0202-007a
■GENERAL
DESCRIPTION
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies. A delay circuit is built-in to each detector.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-ch open drain output configurations are available.
Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible.
■APPLICATIONS
●Microprocessor
reset circuitry
●Memory
battery back-up circuits
●Power-on
reset circuits
●Power
failure detection
●System
battery life and charge voltage monitors
●Delay
circuitry
■FEATURES
Highly Accurate
: ± 2%
Low Power Consumption
: 1.0μA(TYP.)[ V
IN
=2.0V ]
:
1.6V ~ 6.0V in 0.1V increments
Detect Voltage Range
Operating Voltage Range
: 0.7V ~ 10.0V
Detect Voltage Temperature Characteristics
:±100ppm/℃(TYP.)
Built-In Delay Circuit
:
①
1ms ~ 50ms
②
50ms ~ 200ms
③
80ms ~ 400ms
Output Configuration
: N-ch open drain output or CMOS
Operating Ambient Temperature : -30℃½80℃
Packages
: SOT-23
SOT-89
Environmentally Friendly
: EU RoHS Compliant, Pb Free
* No parts are available with an accuracy of ± 1%
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE
CHARACTERISTICS
●Release
Delay Time vs. Ambient Temperature
N-ch open drain output
Release Delay Time: t
DR
(ms)
Ambient Temperature:Ta(℃)
1/14
XC61F
Series
■ABSOLUTE
MAXIMUM RATINGS
PARAMETER
Input Voltage
Output Current
CMOS
Output Voltage
N-ch open drain
output
SOT-23
Power Dissipation
SOT-89
Operating Ambient Temperature
Storage Temperature
SYMBOL
V
IN
I
OUT
V
OUT
Pd
Topr
Tstg
RATINGS
V
SS
-0.3~12.0
50
V
SS
-0.3 ~ V
IN
+ 0.3
V
SS
-0.3 ~ 9
250
500
-30½+80
-40½+125
Ta = 25℃
UNITS
V
mA
V
mW
℃
℃
■ELECTRICAL
CHARACTERISTICS
PARAMETER
Detect Voltage
Hysteresis Width
SYMBOL
V
DF
V
HYS
V
IN
= 1.5V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
DF
= 1.6V to 6.0V
V
IN
= 1.0V
V
IN
= 2.0V
N-ch V
DS
=0.5V V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
P-ch V
DS
=2.1V
V
IN
= 8.0V
(CMOS Output)
V
IN
=V
DF
x 0.9V, V
OUT
=0V
I
LEAK
V
IN
= 10.0V，V
OUT
=10.0V
∆V
DF
/
(∆Topr½V
DF
)
t
DR
-30℃≦Topr≦80℃
-
-
50
80
1
0.01
±100
-
0.1
-
200
400
50
ppm/℃
CONDITIONS
MIN.
V
DF(T)
x 0.98
V
DF
x 0.02
-
-
-
-
-
0.7
1.0
3.0
5.0
6.0
7.0
-
-
TYP.
V
DF(T)
V
DF
x 0.05
0.9
1.0
1.3
1.6
2.0
-
2.2
7.7
10.1
11.5
13.0
-10.0
-0.01
MAX.
V
DF(T)
x 1.02
V
DF
x 0.08
2.6
3.0
3.4
3.8
4.2
10.0
-
-
-
-
-
-2.0
-
μA
UNITS
V
V
Ta = 25℃
CIRCUIT
①
①
Supply Current
I
SS
μA
②
Operating Voltage
V
IN
V
①
③
mA
Output Current
I
OUT
④
CMOS Output
(P-ch)
Leak
Current
N-ch Open
Drain Output
Detect Voltage
Temperature
Characteristics
Release Delay Time
(V
DR
→
V
OUT
inversion)
③
①
V
IN
changes from 0.6V to 10V
ms
⑤
V
DF
(T): Setting detect voltage value
Release Voltage: V
DR
= V
DF
+ V
HYS
* Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available.
Note: The power consumption during power-start to output being stable (release operation) is 2μA greater than it is after that period
(completion of release operation) because of delay circuit through current.
4/14
XC61F
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
①
When a voltage higher than the release voltage (V
DR
) is applied to the voltage input pin (V
IN
), the voltage will gradually
fall. When a voltage higher than the detect voltage (V
DF
) is applied to VIN, output (V
OUT
) will be equal to the input at
VIN.
Note that high impedance exists at V
OUT
with the N-ch open drain output configuration. If the pin is pulled up, V
OUT
will
be equal to the pull up voltage.
When V
IN
falls below V
DF
, V
OUT
will be equal to the ground voltage (V
SS
) level (detect state). Note that this also applies
to N-ch open drain output configurations.
When V
IN
falls to a level below that of the minimum operating voltage (V
MIN
) output will become unstable. Because
the output pin is generally pulled up with configurations, output will be equal to pull up voltage.
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), V
OUT
will be equal to V
SS
until V
IN
reaches the V
DR
level.
Although V
I
N will rise to a level higher than V
DR
, V
OUT
maintains ground voltage level via the delay circuit.
Following transient delay time, V
IN
will be output at V
OUT
. Note that high impedance exists with the N-ch open drain
output configuration and that voltage will be dependent on pull up.
②
③
④
⑤
⑥
Notes:
1. The difference between V
DR
and V
DF
represents the hysteresis range.
2. Release delay time (t
DR
) represents the time it takes for V
IN
to appear at V
OUT
once the said voltage has exceeded the
V
DR
level.
●Timing
Chart
Release Delay
(t
DLY
)
(t
DR
)
Time
5/14
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