VCXO Jitter Attenuator &
FemtoClock
®
NG Multiplier
813N252I-04
Datasheet
General Description
The 813N252I-04 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation. The device contains two internal frequency
multiplication stages that are cascaded in series. The first stage is a
VCXO PLL that is optimized to provide reference clock jitter
attenuation. The second stage is a FemtoClock
®
NG frequency
multiplier that provides the low jitter, high frequency Ethernet output
clock that easily meets Gigabit and 10 Gigabit Ethernet jitter
requirements. Pre-divider and output divider multiplication ratios are
selected using device selection control pins. The multiplication ratios
are optimized to support most common clock rates used in PDH,
SONET and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of the PLL
loop bandwidth and damping characteristics. The device is
packaged in a space-saving 32-VFQFN package and supports
industrial temperature range.
Features
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Fourth generation FemtoClock® Next Generation (NG)
technology
One LVPECL output pair and one LVDS output pair
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
Absolute pull range: 100ppm
FemtoClock NG VCO frequency: 625MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.3ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_OUT
XTAL_IN
nCLK0
nCLK1
CLK0
CLK1
V
CCX
32 31 30 29 28 27 26 25
LF1
LF0
1
2
24
V
EE
V
CC
23 nQB
22
21
QB
V
CCO
ISET 3
V
EE
4
CLK_SEL
V
CC
5
6
20 nQA
19 QA
18
17
9
PDSEL_2
RESERVED 7
V
EE
8
10 11 12 13 14 15 16
ODBSEL_1
ODBSEL_0
ODASEL_1
PDSEL_1
PDSEL_0
V
CC
V
CCA
V
EE
ODASEL_0
813N252I-04
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 11, 2015
813N252I-04 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3
4, 8, 18, 24
5
6, 12, 27
7
9,
10,
11
13
14,
15
16,
17
19, 20
21
22, 23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
PDSEL_2,
PDSEL_1,
PDSEL_0
V
CCA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA, nQA
V
CCO
QB, nQB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
CCX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Reserved
Input
Power
Input
Input
Output
Power
Output
Input
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Description
Loop filter connection node pins. LF0 is the output. LF1 is the input.
Charge pump current setting pin.
Negative supply pins.
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects CLK0,
nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Reserve pin. Do not connect.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for QB, nQB outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for QA, nQA outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Output supply pin.
Differential clock outputs. LVPECL interface levels.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply pin for the XTAL oscillator regulator.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2015 Integrated Device Technology, Inc.
3
Revision C, December 11, 2015
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