PTN3460
eDP to LVDS bridge IC
Rev. 4 — 12 March 2014
Product data sheet
1. General description
PTN3460 is an (embedded) DisplayPort to LVDS bridge device that enables connectivity
between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes
the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and
transmits processed stream in LVDS format.
PTN3460 has two high-speed ports: Receive port facing DP Source (for example,
CPU/GPU/chip set), Transmit port facing the LVDS receiver (for example., LVDS display
panel controller). The PTN3460 can receive DP stream at link rate 1.62 Gbit/s or
2.7 Gbit/s and it can support 1-lane or 2-lane DP operation. It interacts with DP source via
DP Auxiliary (AUX) channel transactions for DP link training and setup.
It supports single bus or dual bus LVDS signaling with color depths of 18 bits per pixel or
24 bits per pixel and pixel clock frequency up to 112 MHz. The LVDS data packing can be
done either in VESA or JEIDA format. Also, the DP AUX interface transports
I
2
C-over-AUX commands and support EDID-DDC communication with LVDS panel. To
support panels without EDID ROM, the PTN3460 can emulate EDID ROM behavior
avoiding specific changes in system video BIOS.
PTN3460 provides high flexibility to optimally fit under different platform environments. It
supports three configuration options: multi-level configuration pins, DP AUX interface, and
I
2
C-bus interface.
PTN3460 can be powered by either 3.3 V supply only or dual supplies (3.3 V/1.8 V) and is
available in the HVQFN56 7 mm
7 mm package with 0.4 mm pitch.
2. Features and benefits
2.1 Device features
Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility
in firmware updates
LVDS panel power-up (/down) sequencing control
Firmware controlled panel power-up (/down) sequence timing parameters
No external timing reference needed
EDID ROM emulation to support panels with no EDID ROM
Supports EDID structure v1.3
On-chip EDID emulation up to seven different EDID data structures
eDP complying PWM signal generation or PWM signal pass through from eDP source
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
2.2 DisplayPort receiver features
Compliant to DP v1.2 and v1.1a
Compliant to eDP v1.2 and v1.1
Supports Main Link operation with 1 or 2 lanes (default mode is 2-lane operation)
Supports Main Link rate: Reduced Bit Rate (1.62 Gbit/s) and High Bit Rate (2.7 Gbit/s)
Supports 1 Mbit/s AUX channel
Supports Native AUX and I
2
C-over-AUX transactions
Supports down spreading to minimize EMI
Integrated 50
termination resistors provide impedance matching on both Main Link
lanes and AUX channel
High performance Auto Receive Equalization enabling optimal channel compensation,
device placement flexibility and power saving at CPU/GPU
Supports eDP authentication options: Alternate Scrambler Seed Reset (ASSR) and
Alternate Framing
Supports Fast Link training and Full Link training
Supports DisplayPort symbol error rate measurements
2.3 LVDS transmitter features
Compatible with ANSI/TIA/EIA-644-A-2001 standard
Supports RGB data packing as per JEIDA and VESA data formats
Supports pixel clock frequency from 25 MHz to 112 MHz
Supports single LVDS bus operation up to 112 mega pixels per second
Supports dual LVDS bus operation up to 224 mega pixels per second
Supports color depth options: 18 bpp, 24 bpp
Programmable center spreading of pixel clock frequency to minimize EMI
Supports 1920
1200 at 60 Hz resolution in dual LVDS bus mode
Programmable LVDS signal swing to pre-compensate for channel attenuation or allow
for power saving
Supports PCB routing flexibility by programming for:
LVDS bus swapping
Channel swapping
Differential signal pair swapping
Supports Data Enable polarity programming
DDC control for EDID ROM access – I
2
C-bus interface up to 400 kbit/s
2.4 Control and system features
Device programmability
Multi-level configuration pins enabling wider choice
I
2
C-bus slave interface supporting Standard-mode (100 kbit/s) and
Fast-mode (400 kbit/s)
Power management
Low-power state: DP AUX command-based Low-power mode (SET POWER)
Deep power-saving state via a dedicated pin
PTN3460
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 12 March 2014
2 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
2.5 General
Power supply: with on-chip regulator
3.3 V
10 % (integrated regulator switched on)
3.3 V
10 %, 1.8 V
5 % (integrated regulator switched off)
ESD: 8 kV HBM, 1 kV CDM
Operating temperature range: 0
C
to 70
C
HVQFN56 package 7 mm
7 mm, 0.4 mm pitch; exposed center pad for thermal relief
and electrical ground
3. Applications
AIO platforms
Notebook platforms
Netbooks/net tops
4. System context diagram
Figure 1
illustrates the PTN3460 usage.
notebook or AIO platform
CPU/GPU/
CHIP SET
eDP
PTN3460
DP to LVDS
BRIDGE
LVDS
cable
LVDS PANEL
MOTHERBOARD
002aaf831
Fig 1.
PTN3460 context diagram
5. Ordering information
Table 1.
Ordering information
Topside mark
PTN3460BS
[3]
Package
Name
PTN3460BS/Fx
[1][2]
HVQFN56
Description
plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 7
7
0.85 mm
[4]
;
0.4 mm pitch
Version
SOT949-2
Type number
[1]
[2]
PTN3460BS/Fx is firmware-specific, where the ‘x’ indicates the firmware version.
Notes on firmware and marking:
a) Firmware versions are not necessarily backwards compatible.
b) Box/reel labels will indicate the firmware version via the orderable part number (for example, labeling will indicate PTN3460BS/F1 for
firmware version 1). A sample label is illustrated in
Figure 8.
[3]
[4]
Topside marking is limited to PTN3460BS and will not indicate the firmware version.
Maximum package height is 1 mm.
PTN3460
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 12 March 2014
3 of 32
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Product data sheet
Rev. 4 — 12 March 2014
4 of 32
PTN3460
6. Block diagram
NXP Semiconductors
supply
PTN3460
RX PHY
ANALOG
SUBSYSTEM
DP0_P,
DP0_N
DIFF CDR,
RCV S2P
RX PHY DIGITAL
DE-SCRAM
ISOCHRONOUS LINK
R[7:0]
INTERFACE DE-SKEWING
G[7:0]
MAIN
STREAM
B[7:0]
H, V
sync
LVDS
DIGITAL
SUBSYSTEM
LVDS
PHY
SUBSYSTEM
LVS[A:D]E_P,
LVS[A:D]E_N
LVSCKE_P,
LVSCKE_N
LVS[A:D]O_P,
LVS[A:D]O_N
LVSCKO_P,
LVSCKO_N
PVCCEN
DPCD
REGISTERS
SYSTEM
CONTROLLER
I
2
C-BUS
CONTOL
INTERFACE
NON-
VOLATILE
MEMORY
BKLTEN
EDID
EMULATION
DDC
INTERFACE
PWMO
10b/8b
TIME
CONV.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
TIMING RECOVERY
V
bias
DP1_P,
DP1_N
DIFF CDR,
RCV S2P
DE-SCRAM
10b/8b
V
bias
RCV
AUX_P,
AUX_N
MANCHESTER
CODEC
DRV
AUX
CONTROL
DDC_SCL
DDC_SDA
V
bias
HPDRX
002aaf832
EPS_N
PD_N RST_N
CFG1
CFG3
DEV_CFG
MS_SDA
eDP to LVDS bridge IC
TESTMODE
CFG2
CFG4
MS_SCL
PTN3460
Fig 2.
Block diagram of PTN3460
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
7. Pinning information
7.1 Pinning
47 LVSCKO_N
46 LVSCKO_P
49 LVSCO_N
44 LVSDO_N
54 LVSAO_N
52 LVSBO_N
48 LVSCO_P
43 LVSDO_P
42 LVSAE_N
41 LVSAE_P
40 LVSBE_N
39 LVSBE_P
38 V
DD(3V3)
37 LVSCE_N
36 LVSCE_P
35 LVSCKE_N
34 LVSCKE_P
33 PVCCEN
32 LVSDE_N
(1)
53 LVSAO_P
51 LVSBO_P
50 V
DD(3V3)
AUX_N
AUX_P
GND
DP0_P
DP0_N
V
DD(1V8)
DP1_P
DP1_N
RST_N
1
2
3
4
5
6
7
8
9
55 n.c.
terminal 1
index area
PTN3460BS
PD_N 10
HPDRX 11
DEV_CFG 12
V
DD(3V3)
13
V
DD(3V3)
14
n.c. 15
n.c. 16
GNDREG 17
GNDREG 18
V
DD(1V8)
19
TESTMODE 20
CFG1 21
CFG2 22
CFG3 23
MS_SDA 24
MS_SCL 25
BKLTEN 26
CFG4 27
PWMO 28
45 V
DD(1V8)
56 EPS_N
31 LVSDE_P
30 DDC_SDA
29 DDC_SCL
002aaf833
Transparent top view
(1) Center pad is connected to PCB ground plane for electrical grounding and thermal relief.
Fig 3.
Pin configuration for HVQFN56
Refer to
Section 13 “Package outline”
for package and pin dimensions.
PTN3460
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 12 March 2014
5 of 32
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