PD‐97661
9A Highly Integrated SupIRBuck
TM
Single‐Input Voltage, Synchronous Buck Regulator
-1-
IR3899
FEATURES
Single 5V to 21V application
Wide Input Voltage Range from 1.0V to 21V with
external Vcc
Output Voltage Range: 0.5V to 0.86× Vin
Enhanced Line/Load Regulation with Feed‐Forward
Programmable Switching Frequency up to 1.5MHz
Internal Digital Soft‐Start/Soft‐Stop
Enable input with Voltage Monitoring Capability
Thermally Compensated Current Limit with robust
hiccup mode over current protection
Smart internal LDO to improve light load and full
load efficiency
External Synchronization with Smooth Clocking
Enhanced Pre‐Bias Start‐Up
Precision Reference Voltage (0.5V+/‐0.5%) with
margining capability
Vp for Tracking Applications (Source/Sink Capability
+/‐9A)
Integrated MOSFET drivers and Bootstrap Diode
Thermal Shut Down
Programmable Power Good Output with tracking
capability
Monotonic Start‐Up
Operating temp: ‐40
o
C < Tj < 125
o
C
Small Size: 4mm x 5mm PQFN
Lead‐free, Halogen‐free and RoHS Compliant
DESCRIPTION
The IR3899 SupIRBuck
TM
is an easy‐to‐use, fully integrated
and highly efficient DC/DC regulator. The onboard PWM
controller and MOSFETs make IR3899 a space‐efficient
solution, providing accurate power delivery.
IR3899 is a versatile regulator which offers programmable
switching frequency and the fixed internal current limit
while operates in wide input and output voltage range.
The switching frequency is programmable from 300kHz to
1.5MHz for an optimum solution.
It also features important protection functions, such as
Pre‐Bias startup, thermally compensated current limit,
over voltage protection and thermal shutdown to give
required system level security in the event of fault
conditions.
APPLICATIONS
Netcom Applications
Embedded Telecom Systems
Server Applications
Storage Applications
Distributed Point of Load Power Architectures
BASIC APPLICATION
98
96
94
Efficiency (%)
92
90
88
86
84
82
80
78
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
12Vin,Internal bias,Frequency 600KHz
Figure 1: IR3899 Basic Application Circuit
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JANUARY 18, 2013 |DATA SHEET | 3.6
1.2Vout
3.3Vout
Figure 2: IR3899 Efficiency
Load Current (A)
PD‐97661
9A Highly Integrated SupIRBuck
TM
Single‐Input Voltage, Synchronous Buck Regulator
-2-
IR3899
Part Number
IR3899MTR1PBF
IR3899MTRPBF
ORDERING INFORMATION
IR3899
―
Package
M
M
Tape & Reel Qty
750
4000
PBF – Lead Free
TR/TR1 – Tape and Reel
M – Package Type
PIN DIAGRAM
4mm x 5mm POWER QFN
TOP VIEW
PV
in
SW
PGND
13
12
11
Boot
14
Enable
15
V
P
16
GND
10
Vcc/LDO_Out
17
9
V
in
8
V
sns
2
3
4
5
6
7
1
JA
½
32
o
C
/
W
J
-
PCB
½
2
o
C
/
W
2
JANUARY 18, 2013 |DATA SHEET | 3.6
PD‐97661
9A Highly Integrated SupIRBuck
TM
Single‐Input Voltage, Synchronous Buck Regulator
-3-
IR3899
BLOCK DIAGRAM
Figure 3: IR3899 Simplified Block Diagram
3
JANUARY 18, 2013 |DATA SHEET | 3.6
PD‐97661
9A Highly Integrated SupIRBuck
TM
Single‐Input Voltage, Synchronous Buck Regulator
-4-
IR3899
PIN DESCRIPTIONS
PIN #
1
PIN NAME
Fb
PIN DESCRIPTION
Inverting input to the error amplifier. This pin is connected directly to the output
of the regulator via resistor divider to set the output voltage and provide
feedback to the error amplifier.
Internal reference voltage , it can be used for margining operation also. In
normal mode and sequencing mode, a 100pF ceramic capacitor is recommended
between this pin and Gnd. In tracking mode operation, Vref should be tied to
Gnd.
Output of error amplifier. An external resistor and capacitor network is typically
connected from this pin to Fb to provide loop compensation.
Signal ground for internal reference and control circuitry.
Multi‐function pin to set switching frequency. Use an external resistor from this
pin to Gnd to set the free‐running switching frequency. An external clock signal
can be connected to this pin through a diode so that the device’s switching
frequency is synchronized with the external clock.
Soft start/stop control. A high logic input enables the device to go into the
internal soft start; a low logic input enables the output soft discharged. Pull this
pin to Vcc if this function is not used.
Power Good status pin. Output is open drain. Connect a pull up resistor (49.9k)
from this pin to the voltage lower than or equal to the Vcc.
Sense pin for over‐voltage protection and PGood. It is optional to tie this pin to
FB pin directly instead of using a resistor divider from Vout.
Input voltage for Internal LDO. A 1.0µF capacitor should be connected between
this pin and PGnd. If external supply is connected to Vcc/LDO_Out pin, this pin
should be shorted to Vcc/LDO_out pin.
Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum
2.2µF cap from this pin to PGnd.
Power Ground. This pin serves as a separated ground for the MOSFET drivers
and should be connected to the system’s power ground plane.
Switch node. This pin is connected to the output inductor.
Input voltage for power stage.
Supply voltage for high side driver, a 100nF capacitor should be connected
between this pin and SW pin.
Enable pin to turn on and off the device, if this pin is connected to PVin pin
through a resistor divider, input voltage UVLO can be implemented.
Input to error amplifier for tracking purposes. In the normal operation, it is left
floating and no external capacitor is required. In the sequencing or the tracking
mode operation, an external signal can be applied as the reference.
Signal ground for internal reference and control circuitry.
2
Vref
3
4
5
Comp
Gnd
Rt/Sync
6
7
8
9
10
11
12
13
14
15
16
17
S_Ctrl
PGood
Vsns
Vin
Vcc/LDO_Out
PGnd
SW
PVin
Boot
Enable
Vp
Gnd
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JANUARY 18, 2013 |DATA SHEET | 3.6
PD‐97661
9A Highly Integrated SupIRBuck
TM
Single‐Input Voltage, Synchronous Buck Regulator
-5-
IR3899
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
PVin, Vin
VCC/LDO_Out
Boot
SW
Boot to SW
S_Ctrl, PGood
Other Input/Output Pins
PGnd to Gnd
Storage Temperature Range
Junction Temperature Range
ESD Classification (HBM JESD22‐A114)
Moisture Sensitivity Level
‐0.3V to 25V
‐0.3V to 8V (Note 2)
‐0.3V to 33V
‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns)
‐0.3V to VCC + 0.3V (Note 1)
‐0.3V to VCC + 0.3V (Note 1)
‐0.3V to +3.9V
‐0.3V to +0.3V
‐55°C to 150°C
‐40°C to 150°C (Note 2)
2kV
JEDEC Level 2@260°C
Note 1: Must not exceed 8V
Note 2: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C
5
JANUARY 18, 2013 |DATA SHEET | 3.6
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