PD - 95085A
IRLR/U3103PbF
Logic-Level Gate Drive
l
Ultra Low On-Resistance
l
Surface Mount (IRLR3103)
l
Straight Lead (IRLU3103)
l
Advanced Process Technology
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Fast Switching
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Fully Avalanche Rated
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Lead-Free
Description
l
HEXFET
®
Power MOSFET
D
V
DSS
= 30V
R
DS(on)
= 0.019Ω
G
S
I
D
= 55A
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
D-PAK
TO-252AA
I-PAK
TO-251AA
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
55
39
220
107
0.71
± 16
240
34
11
5.0
-55 to + 175
300 (1.6mm from case )
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
R
θJA
Junction-to-Case
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
Typ.
–––
–––
–––
Max.
1.4
50
110
Units
°C/W
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1
12/7/04
IRLR/U3103PbF
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
Min. Typ. Max. Units
Conditions
30
––– –––
V
V
GS
= 0V, I
D
= 250µA
––– 0.037 ––– V/°C Reference to 25°C, I
D
= 1mA
––– ––– 0.019
V
GS
= 10V, I
D
= 33A
Ω
––– ––– 0.024
V
GS
= 4.5V, I
D
= 25A
1.0
––– –––
V
V
DS
= V
GS
, I
D
= 250µA
23
––– –––
S
V
DS
= 25V, I
D
= 34A
––– ––– 25
V
DS
= 30V, V
GS
= 0V
µA
––– ––– 250
V
DS
= 18V, V
GS
= 0V, T
J
= 150°C
––– ––– 100
V
GS
= 16V
nA
––– ––– -100
V
GS
= -16V
––– ––– 50
I
D
= 34A
––– ––– 14
nC V
DS
= 24V
––– ––– 28
V
GS
= 4.5V, See Fig. 6 and 13
–––
9.0 –––
V
DD
= 15V
––– 210 –––
I
D
= 34A
ns
–––
20 –––
R
G
= 3.4Ω, V
GS
= 4.5V
–––
54 –––
R
D
= 0.43Ω, See Fig. 10
Between lead,
–––
4.5
–––
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
and center of die contact
––– 1600 –––
V
GS
= 0V
––– 640 –––
pF
V
DS
= 25V
––– 320 –––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 55
showing the
A
G
integral reverse
––– ––– 220
p-n junction diode.
S
––– ––– 1.3
V
T
J
= 25°C, I
S
= 28A, V
GS
= 0V
––– 81 120
ns
T
J
= 25°C, I
F
= 34A
––– 210 310
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
V
DD
= 15V, starting T
J
= 25°C, L = 300µH
R
G
= 25Ω, I
AS
= 34A. (See Figure 12)
Pulse width
≤
300µs; duty cycle
≤
2%
Calculated continuous current based on maximum allowable junction
This is applied for I-PAK, L
S
of D-PAK is measured between lead and
center of die contact
Uses IRL3103 data and test conditions
temperature; Package limitation current = 20A
I
SD
≤
34A, di/dt
≤
140A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRLR/U3103PbF
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
1000
TOP
I
D
, Drain-to-Source Current (A)
100
I
D
, Drain-to-Source Current (A)
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
100
10
10
2.5V
2.5V
1
0.1
20µs PULSE WIDTH
T
J
= 25°C
10
1
100
A
1
0.1
20µs PULSE WIDTH
T
J
= 175°C
1
10
100
A
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
1000
2.0
I
D
= 56A
I
D
, Drain-to-Source Current (A)
T
J
= 25°C
100
1.5
T
J
= 175°C
1.0
10
0.5
1
2.0
3.0
4.0
5.0
V
DS
= 15V
20µs PULSE WIDTH
6.0
7.0
8.0
9.0
A
0.0
-60 -40 -20
0
20
40
60
V
GS
= 10V
80 100 120 140 160 180
A
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRLR/U3103PbF
3200
2800
2400
2000
1600
1200
800
400
0
1
10
100
V
GS
, Gate-to-Source Voltage (V)
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
, C
ds
SHORTED
C
rss
= C
gd
C
iss C
oss
= C
ds
+ C
gd
15
I
D
= 34A
V
DS
= 24V
V
DS
= 15V
12
C, Capacitance (pF)
C
oss
9
C
rss
6
3
A
0
0
10
20
30
FOR TEST CIRCUIT
SEE FIGURE 13
40
50
60
70
A
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10µs
100
100µs
100
T
J
= 175°C
T
J
= 25°C
I
D
, Drain Current (A)
1ms
10
10ms
10
0.4
0.8
1.2
1.6
2.0
V
GS
= 0V
2.4
A
1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
2.8
100
A
V
SD
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRLR/U3103PbF
60
LIMITED BY PACKAGE
50
V
DS
V
GS
R
G
R
D
D.U.T.
+
I
D
, Drain Current (A)
40
-
V
DD
5.0V
30
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
20
Fig 10a.
Switching Time Test Circuit
V
DS
90%
10
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( °C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
10
Thermal Response (Z
thJC
)
1
D = 0.50
0.20
0.10
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
t
2
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
0.1
0.05
0.02
0.01
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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