Ordering number : :ENA2170A
Ordering number ENA2170
LC89075WA
CMOS LSI
Digital Audio Interface Receiver
with Stereo ADC and Audio Selector
1. Overview
http://onsemi.com
The LC89075WA is a digital audio interface receiver that demodulates signals according to the data transfer format
between digital audio devices via IEC60958/61937 and JEITA CPR-1205 and supports demodulation sampling
frequencies of up to 192kHz.
The LC89075WA also incorporates a high performance 24-bit single-end input
stereo analog to digital converter
that supports sampling frequencies of up to 96kHz, and an audio selector that can support 8-channel data.
The LC89075WA is a complete analog and digital front-end for use in various systems including AV receivers,
digital TVs, and DVD recorders.
2. Features
2.1 ADC
stereo ADC
Built-in anti-aliasing digital filter
Single-end input (3Vp-p)
Built-in digital HPF for canceling DC offset
Built-in PGA (-4.5dB to 6dB/1.5dB step)
Built-in soft mute and attenuator (0dB to -63.5dB/0.25dB step, -)
Sampling frequency: 8kHz to 96kHz
SQFP64(10X10)
Master clock: 512fs, 256fs (master/slave)
Audio data output interface: 24-bit I
2
S/left justified
Analog audio data detection (threshold level: -30dB to -60dB/adjustable in 2dB steps)
2.2 DIR
S/PDIF demodulation process according to IEC60958/61937 and JEITA CPR-1205
Reception frequency: 32kHz to 192kHz (PLL lock range)
Built-in 15:3 digital data selector enables separate selection of data to be demodulated and data output to pins.
- S/PDIF input: Up to 15 systems that support TTL (3 systems can support coaxial)
- S/PDIF output: Possible to select two systems of pin outputs, and one system of demodulation data
Possible to limit the acceptable sampling frequency and set the no-signal input status when the reception range is
exceeded.
Built-in a PLL low clock jitter and an oscillation amplifier.
Outputs the monitor signal that is switched between PLL and crystal.
Outputs master clock: 512fs, 256fs and 128fs (with automatic adjustment function)
Audio data output interface: 24-bit I
2
S/left justified
Outputs DTS-CD detection flag.
Outputs interrupt signal for microcontroller.
Calculates input sampling frequency.
Reads IEC61937 burst preamble PC data from microcontroller.
Reads first 40 bits of channel status from microcontroller.
Outputs bit 1 (non-PCM data delimiter bit) and main bits of channel status to the pin.
ORDERING INFORMATION
See detailed ordering and shipping information on page 70 of this data sheet.
Semiconductor Components Industries, LLC, 2013
December, 2013
D1813HK 20131120-S00003/12313HK No.A2170-1/70
LC89075WA
2.3 Other
Built-in audio selector supports up to 8-channel data.
Selector configuration to support 2-ch data:
4-line input
6
and 4-line output
2
Selector configuration to support 6-ch and 2-ch data:
6-line input
1,
4-line input
5
and 6-line output
1
Selector configuration to support 8-ch and 2-ch data:
7-line input
1,
4-line input
4
and 7-line output
1
Possible to take in external error flag, non-PCM flag, and mute flag
PCM digital audio data detection (threshold level: -30dB to -60dB/adjustable in 2dB steps)
SPI microcontroller interface (with automatic increment function)
Built-in power-on reset circuit
Input pin reverse bias control during power-off
Supply voltages:
ADC analog: 4.5 to 5.5V (3.0 to 3.6V possible when not using the ADC)
PLL analog: 3.0 to 3.6V
Digital: 3.0 to 3.6V
Operation guarantee temperature: -30 to 85°C
Package: SQFP64 (lead-free and halogen-free)
Package Dimensions
unit : mm (typ)
12.0
48
49
33
32
0.5
10.0
64
1
0.5
(1.25)
(1.5)
17
16
0.18
0.15
1.7max
0.1
SANYO : SQFP64(10X10)
10.0
12.0
No.A2170-2/70
LC89075WA
4. Pin Assignment
DSTATE
XMODE
ADINR
DGND
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RXIN3A
RXIN2A
RXIN1A
DGND
RXOUT
DVDD
DGND
RXIN8
RXIN7
RXIN6
RXIN5
RXIN4
RXIN3
RXIN2
RXIN1
PVDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
LPF
2
PGND
3
MCKIN
4
BCKIN
5
LRCKIN
6
DATAIN
7
MPIN1
8
MPIN2
9
MPIN3
10 11 12 13 14 15 16
MPIN4
MPIN5
MPIN6
BCKOUT
DATAOUT
MCKOUT
LRCKOUT
32
31
30
29
28
27
XIN
XOUT
XMCK
MPIO4
MPIO3
MPIO2
MPIO1
NPCMF
MUTEB
ERRF
MPOUT4
MPOUT3
MPOUT2
MPOUT1
DVDD
DGND
DGND
26
25
24
23
22
21
20
19
18
17
ADINL
AGND
DVDD
LC89075WA
DVDD
AVDD
VREF
INTB
SCK
CSB
SO
SI
Top view
Figure 4.1 LC89075WA Pin Assignment
No.A2170-3/70
LC89075WA
5. Pin Functions
Table 5.1 Pin Functions
No
1
2
3
Name
LPF
PGND
MCKIN
I
I/O
O
PLL: Loop filter connection pin
PLL: Analog GND
Group A
Group A+B
4
BCKIN
I
Group A
Group A+B
5
LRCKIN
I
Group A
Group A
Group A+B
6
DATAIN
I
Group A
Group A
Group A+B
7
MPIN1
I
Group B
Group A+B
8
MPIN2
I
Group B
Group A+B
9
MPIN3
I
Group B
Group B
Group A+B
10
MPIN4
I
Group B
Group B
Group B
Group A+B
11
MPIN5
I
Group B
Group A+B
12
MPIN6
I
Group B
Group A+B
13
14
15
MCKOUT
BCKOUT
LRCKOUT
O
O
O
: Master clock input pin
: Master clock input pin
: Bit clock input pin
: Bit clock input pin
: LR clock input pin
: DSD data input pin
: LR clock input pin
: 2ch audio data input pin
: DSD data input pin
: 1, 2ch/8ch audio data input pin
: Master clock input pin
: 3, 4ch/8ch audio data input pin
: Bit clock input pin
: 5, 6ch/8ch audio data input pin
: LR clock input pin
: DSD data input pin
: 7, 8ch/8ch audio data input pin
: 2ch audio data input pin
: DSD data input pin
: 1, 2ch/6ch audio data input pin
: External error signal input pin
: 3, 4ch/6ch audio data input pin
: External data mute signal input pin
: 5, 6ch/6ch audio data input pin
: External non-PCM signal input pin
to [MCKOUT], [MPOUT1]
to [MCKOUT]
to [BCKOUT], [MPOUT2]
to [BCKOUT]
to [LRCKOUT], [MPOUT3]
to [LRCKOUT], [MPOUT3]
to [LRCKOUT]
to [DATAOUT], [MPOUT4]
to [DATAOUT], [MPOUT4]
to [DATAOUT]
to [MCKOUT], [MPOUT1]
to [MPOUT1]
to [BCKOUT], [MPOUT2]
to [MPOUT2]
to [LRCKOUT], [MPOUT3]
to [LRCKOUT], [MPOUT3]
to [MPOUT3]
to [DATAOUT], [MPOUT4]
to [DATAOUT], [MPOUT4]
to [DATAOUT]
to [ERRF]
to [MPOUT1]
to [MUTEB]
to [MPOUT2]
to [NPCMF]
from ADC, DIR, [MCKIN], [MPIN1], [MPIO1], [RXIN8]
from ADC, DIR, [BCKIN], [MPIN2], [MPIO2], [RXIN7]
from ADC, DIR, [LRCKIN], [MPIN3], [MPIO3], [RXIN6]
from [LRCKIN], [MPIN3], [MPIO3], [RXIN6]
from ADC, DIR, [DATAIN], [MPIN4], [MPIO4], [RXIN5]
from [DATAIN], [MPIN4], [MPIO4], [RXIN5]
from [MPIN4]
from [DATAIN]
Function
Master clock output pin
Bit clock output pin
LR clock output pin
DSD data output pin
16
DATAOUT
O
2ch audio data output pin
DSD data output pin
1, 2ch/6ch audio data output pin
1, 2ch/8ch audio data output pin
17
18
19
DGND
DVDD
MPOUT1
O
Digital GND
Digital power supply (3.3V)
Master clock output pin
3, 4ch/6ch audio data output pin
3, 4ch/8ch audio data output pin
from ADC, [MCKIN], [MPIN1], [MPIO1], [RXIN8]
from [MPIN5]
from [MPIN1]
from ADC, [BCKIN], [MPIN2], [MPIO2], [RXIN7]
from [MPIN6]
from [MPIN2]
from ADC, [LRCKIN], [MPIN3], [MPIO3], [RXIN6]
from [LRCKIN], [MPIN3], [MPIO3], [RXIN6]
from [MPIN3]
20
MPOUT2
O
Bit clock output pin
5, 6ch/6ch audio data output pin
5, 6ch/8ch audio data output pin
21
MPOUT3
O
LR clock output pin
DSD data output pin
7, 8ch/8ch audio data output pin
Continued on next page.
No.A2170-4/70
LC89075WA
Continued from preceding page.
No
22
Name
MPOUT4
I/O
O
2ch audio data output pin
DSD data output pin
Input S/PDIF through output pin
23
ERRF
O
PLL lock error, data error flag output pin
External error signal output pin
24
MUTEB
O
Clock switching period data mute signal output pin
External data mute signal output pin
25
NPCMF
O
Channel status data delimiter bit (bit 1) output pin
External non-PCM signal output pin
26
MPIO1
O
Channel status data delimiter bit (bit 1) output pin
Microcontroller extended register output pin
I
Master clock input pin (ADC slave operation)
Group C
: Master clock input pin
to ADC, [MPOUT1]
to [MCKOUT], [MPOUT1]
from [MPIN6]
from [MPIN5]
from [MPIN4]
Function
from ADC, [DATAIN], [MPIN4], [MPIO4], [RXIN5]
from [DATAIN], [MPIN4], [MPIO4], [RXIN5]
3.3V tolerance TTL-compatible S/PDIF input pin
27
MPIO2
O
Channel status copy bit output pin
Microcontroller extended register output pin
I
Bit clock input pin (ADC slave operation)
Group C
: Bit clock input pin
to ADC, [MPOUT2]
to [BCKOUT], [MPOUT2]
3.3V tolerance TTL-compatible S/PDIF input pin
28
MPIO3
O
Channel status emphasis information output pin
Microcontroller extended register output pin
I
LR clock input pin (ADC slave operation)
Group C
Group C
: LR clock input pin
: DSD data input pin
to ADC
to [LRCKOUT], [MPOUT3]
to [LRCKOUT], [MPOUT3]
3.3V tolerance TTL-compatible S/PDIF input pin
29
MPIO4
O
Channel status age bit output pin
Microcontroller extended register output pin
2ch audio data output pin (ADC slave operation)
I
Group C
Group C
: 2ch audio data input pin
: DSD data input pin
from ADC
to [DATAOUT], [MPOUT4]
to [DATAOUT], [MPOUT4]
3.3V tolerance TTL-compatible S/PDIF input pin
30
31
32
XMCK
XOUT
XIN
O
O
I
Oscillation amplifier clock output pin
Crystal resonator connection output pin
Crystal resonator connection or external clock input pin
(12.288MHz or 24.576MHz)
33
34
35
DGND
DVDD
XMODE
I
Digital GND
Digital power supply (3.3V)
System reset input pin
(when power-on reset is used: fixed at “H”)
36
37
38
39
40
41
42
43
CSB
SCK
SI
SO
INTB
DSTATE
DVDD
DGND
I
I
I
O
O
O
SPI microcontroller I/F, chip enable input pin
SPI microcontroller I/F, shift clock input pin
SPI microcontroller I/F, write data input pin
SPI microcontroller I/F, read data output pin
SPI microcontroller I/F, interrupt signal output pin
Analog or digital data detection flag output pin
Digital power supply (3.3V)
Digital GND
Continued on next page.
No.A2170-5/70
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