MIC502
Fan Management IC
General Description
The MIC502 is a thermal and fan management IC that
supports the features for NLX/ATX power supplies and
other control applications.
Fan speed is determined by an external temperature
sensor, typically a thermistor-resistor divider, and
(optionally) a second signal, such as the NLX “FanC”
signal. The MIC502 produces a low-frequency pulse-width
modulated output for driving an external motor drive
transistor. Low-frequency PWM speed control allows
operation of standard brushless DC fans at low duty-cycle
for reduced acoustic noise and permits the use of a very
small power transistor. The PWM time base is determined
by an external capacitor.
An open-collector overtemperature fault output is asserted
if the primary control input is driven above the normal
control range.
The MIC502 features a low-power sleep mode with a user-
determined threshold. Sleep mode completely turns off the
fan and occurs when the system is asleep or off (both
control inputs very low). A complete shutdown or reset can
also be initiated by external circuitry as desired.
The MIC502 is available as 8-pin plastic DIP and SOIC
packages in the –40°C to +85°C industrial temperature
range.
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Features
•
•
•
•
•
•
•
•
•
Temperature-proportional fan speed control
Low-cost, efficient PWM fan drive
4.5V to 13.2V IC supply range
Controls any voltage fan
Overtemperature detection with fault output
Integrated fan startup timer
Automatic user-specified sleep mode
Supports low-cost NTC/PTC thermistors
8-pin DIP and SOIC packages
Applications
•
•
•
•
•
•
•
•
NLX and ATX power supplies
Personal computers
File servers
Telecom and networking hardware
Printers, copiers, and office equipment
Instrumentation
Uninterruptible power supplies
Power amplifiers
Typical Application
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
October 6, 2014
Revision 3.0
Micrel, Inc.
MIC502
Ordering Information
Part Number
MIC502YN
MIC502YM
Temperature Range
–40° to +85°C
–40° to +85°C
Package
8-Pin Plastic DIP
8-Pin SOIC
Lead Finish
Pb-Free
Pb-Free
Pin Configuration
8-Pin SOIC (M)
8-Pin DIP (N)
(Top View)
Pin Description
Pin Number
1
Pin Name
VT1
Pin Function
Thermistor 1 (input): Analog input of approximately 30% to 70% of V
DD
produces active duty cycle
of 0% to 100% at driver output (OUT). Connect to external thermistor network (or other
temperature sensor). Pull low for shutdown.
PWM timing capacitor (external component): Positive terminal for the PWM triangle-wave
generator timing capacitor. The recommended CF is 0.1µF for 30Hz PWM operation.
Sleep threshold (input): The voltage on this pin is compared to VT1 and VT2. When V
T1
< V
SLP
and V
T2
< V
SLP
the MIC502 enters sleep mode until V
T1
or V
T2
rises above V
WAKE
. (V
WAKE
= V
SLP
+
V
HYST
). Grounding V
SLP
disables the sleep-mode function.
Ground
Thermistor 2 (input): Analog input of approximately 30% to 70% of V
DD
produces active duty cycle
of 0% to 100% at driver output (OUT). Connect to motherboard fan control signal or second
temperature sensor.
Overtemperature fault (output): Open-collector output (active-low). Indicates overtemperature
fault condition (V
T1
> V
OT
) when active.
Driver output: Asymmetrical-drive active-high complimentary PWM output. Typically connect to
base of external NPN motor control transistor.
Power supply (input): IC supply input; may be independent of fan power supply.
2
CF
3
4
5
VSLP
GND
VT2
6
7
8
/OTF
OUT
VDD
October 6, 2014
2
Revision 3.0
Micrel, Inc.
MIC502
Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
) .................................................... +14V
Output Sink Current (I
OUT(sink)
). .................................... 10mA
Output Source Current (I
OUT(source)
) .............................. 25mA
Input Voltage (any pin) ......................... –0.3V to V
DD
+ 0.3V
Junction Temperature (T
J
) ....................................... +125°C
Lead Temperature (soldering, 5s) .............................. 260°C
Storage Temperature (Ts)......................... –65°C to +150°C
(3)
ESD Rating ................................................. ESD Sensitive
Operating Ratings
(2)
Supply Voltage (V
DD
) .................................. +4.0V to +13.2V
Sleep Voltage (V
SLP
).......................................... GND to V
DD
Temperature Range (T
A
) ............................. –40°C to +85°C
Power Dissipation at +25°C
SOIC .................................................................. 800mW
DIP ..................................................................... 740mW
Derating Factors
SOIC .............................................................. 8.3mW/°C
Plastic DIP ..................................................... 7.7mW/°C
Electrical Characteristics
(4)
4.5V ≤ V
DD
≤ 13.2V ; T
A
= 25°C,
bold
values indicate –40°C≤ T
A
≤ +85°C, unless noted.
(5)
Symbol
I
DD
I
DD(slp)
Parameter
Supply Current, Operating
Supply Current, Sleep
Condition
V
SLP
= GND, /OTF, OUT = open,
C
F
= 0.1µF, V
T1
= V
T2
= 0.7 V
DD
V
T1
= GND, V
SLP
, /OTF, OUT = open,
C
F
= 0.1µF
Min.
Typ.
Max.
1.5
500
Units
mA
µA
Driver Output
t
R
t
F
I
OL
I
OH
I
OS
Output Rise Time,
Note 6
Output Fall Time,
Note 6
Output Sink Current
Output Source Current
Sleep Mode Output Leakage
I
OH
= 10mA
I
OL
= 1mA
V
OL
= 0.5V
4.5V ≤ V
DD
≤ 5.5V, V
OH
= 2.4V
10.8V ≤ V
DD
≤ 13.2V, V
OH
= 3.2V
V
OUT
= 0V
0.9
10
10
1
50
50
µs
µs
mA
mA
mA
µA
Thermistor and Sleep Inputs
V
PWM(max)
V
PWM(span)
V
HYST
V
IL
V
IH
V
OT
I
VT
, I
VSLP
t
RESET
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
5. Part is functional over this V
DD
range. However, it is characterized for operation at 4.5V ≤ V
DD
≤ 5.5V and 10.8V ≤ V
DD
≤ 13.2V ranges. These ranges
correspond to a nominal V
DD
of 5V and 12V, respectively.
6. Guaranteed by design.
7. V
OT
is guaranteed by design to always be higher than V
PWM(max)
.
100% PWM Duty Cycle Input
Voltage
V
PWM(max)
– V
PWM(min)
Sleep Comparator Hysteresis
VT1 Shutdown Threshold
VT1 Startup Threshold
VT1 Overtemperature Fault
Threshold
VT1, VT2, VSLP Input Current
Reset Setup Time
Minimum time V
T1
< V
IL
to guarantee reset.
Note 6
Note 7
67
37
8
70
40
11
73
43
14
0.7
%V
DD
%V
DD
%V
DD
V
V
1.1
74
-2.5
30
77
80
1
%V
DD
µA
µs
October 6, 2014
3
Revision 3.0
Micrel, Inc.
MIC502
Electrical Characteristics
(4)
(Continued)
4.5V ≤ V
DD
≤ 13.2V ; T
A
= 25°C,
bold
values indicate –40°C≤ T
A
≤ +85°C, unless noted.
(5)
Symbol
Oscillator
f
f
MIN
, f
MAX
t
STARTUP
Parameter
Condition
4.5V ≤ V
DD
≤ 5.5V, C
F
= 0.1µF
10.8V ≤ V
DD
≤ 13.2V, C
F
= 0.1µF
Note 8
Min.
Typ.
Max.
Units
Oscillator Frequency,
Note 8
Oscillator Frequency Range
Startup Interval
24
27
15
27
30
30
33
90
Hz
Hz
Hz
s
64/f
Overtemperature Fault Output
V
OL
I
OH
Note:
8. Logic time base and PWM frequency. For other values of C
F
, f(Hz) = 30Hz × (0.1µF ÷ C), where C is measured in µF.
Active (Low) Output Voltage
Off-State Leakage
I
OL
= 2mA
V
/OTF
= V
DD
1
0.3
V
µA
Timing Diagrams
Figure 1. Typical System Behavior
Note A.
Output duty-cycle is initially determined by V
T1
because it is greater than V
T2
.
Note B.
PWM duty-cycle follows V
T1
as it increases.
Note C.
V
T1
drops below V
T2
. V
T2
now determines the output duty-cycle.
Note D.
The PWM duty-cycle follows V
T2
as it increases.
Note E.
Both V
T1
and V
T2
decrease below V
SLP
, but above V
IL
. The device enters sleep mode.
Note F.
The PWM wakes up because one of the control inputs (V
T1
in this case) has risen above V
WAKE
. The startup timer is triggered, forcing OUT high
for 64 clock periods. (V
WAKE
= V
SLP
+ V
HYST
. See the
Electrical Characteristics
section for details).
Note G.
Following the startup interval, the PWM duty-cycle is the higher of V
T1
and V
T2
.
October 6, 2014
4
Revision 3.0
Micrel, Inc.
MIC502
Timing Diagrams (Continued)
Figure 2. MIC502 Typical Power-Up System Behavior
Note H.
At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (t
PWM
). This ensures that the fan will start from a dead
stop.
Note I.
The PWM duty-cycle follows the higher of V
T1
and V
T2
, in this case, V
T1
.
Note J.
The PWM duty-cycle follows V
T1
as it increases.
Note K.
PWM duty-cycle is 100% (OUT constantly on) anytime V
T1
> V
PWM(max)
.
Note L.
/OTF is asserted anytime V
T1
> V
OT
. The fan continues to run at 100% duty-cycle.
Note M.
/OTF is deasserted when V
T1
falls below V
OT
; duty-cycle once again follows V
T1
.
Note N.
Duty-cycle follows V
T1
until V
T1
< V
T2
, at which time V
T2
becomes the controlling input signal. Note that V
T1
is below V
SLP
but above V
IH
; so
normal operation continues. Both V
T1
and V
T2
must be below V
SLP
to active sleep mode.
Note O.
All functions cease when V
T1
< V
IL
; this occurs regardless of the state of V
T2
.
October 6, 2014
5
Revision 3.0
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
