SM802104
ClockWorks™ Fibre Channel
(106.25MHz, 212.5MHz), Ultra-Low Jitter,
LVPECL Frequency Synthesizer
General Description
The SM802104 is a member of the ClockWorks™ family of
devices from Micrel and provides an extremely low-noise
timing solution for Fibre Channel clock signals. It is based
upon a unique, patented RotaryWave
®
architecture that
provides very low phase noise.
The device operates from a 3.3V or 2.5V power supply
and synthesizes LVPECL output clocks at 106.25MHz or
212.5MHz. There are normally two clock outputs, but one
output can be achieved by powering down the second
output with the OE pin. The SM802104 accepts a
26.5625MHz crystal or LVCMOS reference clock.
Data sheets and support documentation can be found on
Micrel’s web site at:
www.micrel.com.
Features
•
Generates one or two LVPECL clock outputs at
106.25MHz or 212.5MHz
•
2.5V or 3.3V operating range
•
Typical phase jitter @ 106.25MHz
(637kHz to 10MHz): 200fs
•
Industrial temperature range
•
Green, RoHS, and PFOS compliant
•
Available in 24-pin 4mm
×
4mm QFN package
Applications
•
Fibre Channel
•
Storage Networking (SAN, NAS)
Block Diagram
ClockWorks is a trademark of Micrel, Inc
RotaryWave is a registered trademark of Multigig, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
April 2011
M9999-042111-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802104
Ordering Information
Part Number
SM802104UMG
SM802104UMGR
Note:
1. Devices are Green, RoHS, and PFOS compliant.
Marking
802104
802104
Shipping
Tube
Tape and Reel
Junction Temperature Range
(1)
-40°C to +85°C
-40°C to +85°C
Package
24-Pin QFN
24-Pin QFN
Pin Configuration
24-Pin QFN (code)
(Top View)
Pin Description
Pin Number
19, 20
22, 23
24
2
Pin Name
/Q1, Q1
/Q2, Q2
VDDO2
VSSO2
Pin Type
O, (DIF)
O, (DIF)
PWR
PWR
Pin Level
LVPECL
LVPECL
Pin Function
Differential Clock Output from Bank 1
106.25MHz or 212.5MHz
Differential Clock Output from Bank 2
106.25MHz or 212.5MHz
Power Supply for Output Bank 2
Power Supply Ground for Output Bank 2
PLL Bypass, Selects Output Source
3
PLL_BYPASS
I, (SE)
LVCMOS
0 = Normal PLL Operation
1 = Output from Input Reference Clock or Crystal
45KΩ pull-down
4
XTAL_SEL
I, (SE)
LVCMOS
Selects PLL Input Reference Source
0 = REF_IN, 1 = XTAL, 45KΩ pull-up
April 2011
2
M9999-042111-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802104
Pin Description (Continued)
Pin Number
5, 11, 16, 18
1
13, 14, 15
17
21
8
9
10
6
7
12
Pin Name
TEST
VDD
VSS
VDDO1
VSSO1
REF_IN
XTAL_IN
XTAL_OUT
FSEL
OE1
OE2
PWR
PWR
PWR
PWR
I, (SE)
I, (SE)
O, (SE)
I, (SE)
I, (SE)
I, (SE)
LVCMOS
12pF crystal
12pF crystal
LVCMOS
LVCMOS
LVCMOS
Pin Type
Pin Level
Pin Function
Factory Test pins, Do not connect anything to these pins.
Core Power Supply
Core Power Supply Ground
Power Supply for Output Bank 1
Power Supply Ground for Output Bank 1
Reference Clock Input
Crystal Reference Input, no load caps needed.
See Fig. 5.
Crystal Reference Output, no load caps needed.
See Fig. 5.
Frequency Select, 1 = 106.25MHz, 0 = 212.5MHz,
45KΩ pull-up
Output Enable, Q1 disables to tri-state,
0 = Disabled, 1 = Enabled, 45KΩ pull-up
Output Enable, Q2 disables to tri-state,
0 = Disabled, 1 = Enabled, 45KΩ pull-up
Application Information
Input Reference
When operating with a crystal input reference, do not apply a switching signal to REF_IN.
Crystal Layout
Keep the layers under the crystal as open as possible.
Do not place switching signals or noisy supplies under the crystal.
Truth Tables
PLL_BYPASS
0
1
−
−
XTAL_SEL
−
−
0
1
Output Frequency
(MHz)
212.5
106.25
INPUT
−
−
REF_IN
XTAL
OUTPUT
PLL
XTAL/REF_IN
−
−
FSEL
0
1
April 2011
3
M9999-042111-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802104
Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
, V
DDOx
) ........................................+4.6V
Input Voltage (V
IN
) ............................... -0.50V to V
DD
+ 0.5V
Lead Temperature (soldering, 20s)............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (T
s
) ..........................-65°C to
+150°C
Operating Ratings
(2)
Supply Voltage (V
DD
, V
DDOx
)................. +2.375V to +3.465V
Ambient Temperature (T
A
)........................... -40°C to +85°C
Junction Thermal Resistance
(3)
QFN (θ
JA
)
Still-Air......................................................... 50°C/W
QFN (ψ
JB
)
Junction-to-Board ....................................... 30°C/W
DC Electrical Characteristics
(4)
V
DD
= V
DDO1/2
= 3.3V
±5%
or 2.5V
±5%
V
DD
= 3.3V
±5%,
V
DDO1/2
= 3.3V
±5%
or 2.5V
±5%
T
A
= -40°C to
+85°C.
Symbol
V
DD
, V
DDOx
V
DD
, V
DDOx
I
DD
REF_IN
Parameter
2.5V Operating Voltage
3.3V Operating Voltage
106.25MHz - 1 output
Supply current V
DD
+ V
DDO
XTAL_SEL = 0
Outputs open
Supply current V
DD
+ V
DDO
XTAL_SEL = 1
Outputs open
106.25MHz - 2 outputs
212.5MHz - 1 output
212.5MHz - 2 outputs
106.25MHz - 1 output
106.25MHz - 2 outputs
212.5MHz - 1 output
212.5MHz - 2 outputs
Condition
Min.
2.375
3.135
Typ.
2.5
3.3
82
98
92
111
93
109
103
122
Max.
2.625
3.465
105
127
119
145
120
142
134
159
mA
mA
Units
V
V
I
DD
XTAL
LVPECL DC Electrical Characteristics
(4)
V
DD
= V
DDO1/2
= 3.3V
±5%
or 2.5V
±5%
V
DD
= 3.3V
±5%,
V
DDO1/2
= 3.3V
±5%
or 2.5V
±5%
T
A
= -40°C to
+85°C.
R
L
= 50Ω to V
DDO
- 2V
Symbol
V
OH
V
OL
V
SWING
Notes:
1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
Parameter
Output High Voltage
Output Low Voltage
Output Voltage Swing
Condition
Min.
V
DDO
– 1.145
V
DDO
– 1.945
0.6
Typ.
V
DDO
– 0.97
V
DDO
– 1.77
0.8
Max.
V
DDO
– 0.845
V
DDO
– 1.645
1.0
Units
V
V
V
2.
3.
4.
April 2011
4
M9999-042111-A
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SM802104
LVCMOS (PLL_BYPASS, XTAL_SEL, OE1/2, FSEL) DC Electrical Characteristics
(4)
V
DD
= 3.3V
±5%,
or 2.5V
±5%,
T
A
= -40°C to
+85°C.
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
Condition
Min.
2
-0.3
Typ.
Max.
V
DD
+ 0.3
0.8
150
Units
V
V
μA
μA
REF_IN DC Electrical Characteristics
(4)
V
DD
= 3.3V
±5%,
or 2.5V
±5%,
T
A
= -40°C to
+85°C.
Symbol
V
IH
V
IL
I
IN
Parameter
Input High Voltage
Input Low Voltage
Input Current
XTAL_SEL = V
IL
, V
IN
= 0V to V
DD
XTAL_SEL = V
IH
, V
IN
= V
DD
Condition
Min.
1.1
-0.3
-5
20
Typ.
Max.
V
DD
+ 0.3
0.6
5
Units
V
V
μA
µA
Crystal Characteristics
NDK NX2520SA
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitor, C0
Correlation Drive Level
Condition
12pF Load
Min.
Typ.
26.5625
3
100
50
7
300
Max.
Units
MHz
Ω
pF
uW
Fundamental, Parallel Resonant
April 2011
5
M9999-042111-A
hbwhelp@micrel.com
or (408) 955-1690
FPGA/CPLD
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