PCI Express
™
Clock Generator
Datasheet
841S04
General Description
The 841S04 is a PLL-based clock generator specifically designed for
PCI Express™ Clock Generation applications. This device
generates a 100MHz HCSL clock. The device offers a HCSL (Host
Clock Signal Level) clock output from a clock input reference of
25MHz. The input reference may be derived from an external source
or by the addition of a 25MHz crystal to the on-chip crystal oscillator.
An external reference may be applied to the XTAL_IN pin with the
XTAL_OUT pin left floating.
The device offers spread spectrum clock output for reduced EMI
applications. An I
2
C bus interface is used to enable or disable spread
spectrum operation as well as select either a down spread value of
-0.35% or -0.5%.
Features
•
•
•
•
•
•
•
•
•
•
•
Four 0.7V current mode differential HCSL output pairs
Crystal oscillator interface: 25MHz
Output frequency: 100MHz
RMS period jitter: 3ps (maximum)
Output skew: 70ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
I
2
C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
25MHz
Pin Assignment
4
XTAL_IN
OSC
XTAL_OUT
SDATA
Pullup
SCLK
Pullup
PLL
Divider
Network
SRCT[1:4]
SRCC[1:4]
4
I
2
C
Logic
4
IREF
SRCT3
SRCC3
V
SS
V
DD
SRCT2
SRCC2
SRCT1
SRCC1
V
SS
V
DD
V
SS
IREF
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SRCC4
SRCT4
V
DD
SDATA
SCLK
XTAL_OUT
XTAL_IN
V
DD
V
SS
nc
V
DDA
V
SS
841S04
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision C, July 15, 2016
841S04 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3, 9, 11, 13, 16
4, 10, 17, 22
5, 6
7, 8
12
14
15
18,
19
20
21
23, 24
Name
SRCT3, SRCC3
V
SS
V
DD
SRCT2, SRCC2
SRCT1, SRCC1
IREF
V
DDA
nc
XTAL_IN,
XTAL_OUT
SCLK
SDATA
SRCT4, SRCC4
Type
Output
Power
Power
Output
Output
Input
Power
Unused
Input
Input
I/O
Output
Pullup
Pullup
Description
Differential output pair. HCSL interface levels.
Ground for core and SRC outputs.
Power supply for core and SRC outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475
) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx clock
outputs.
Power supply for PLL.
No connect.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
I
2
C SMBus compatible SCLK. This pin has an internal pullup resistor, but is in
high-impedance in power-down mode. LVCMOS/LVTTL interface levels.
I
2
C SMBus compatible SDATA. This pin has an internal pullup resistor, but is
in high-impedance in power-down mode. LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
©2016 Integrated Device Technology, Inc.
2
Revision C, July 15, 2016
841S04 Datasheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock output
buffers, can be individually enabled or disabled. The registers
associated with the Serial Data Interface initialize to their default
setting upon power-up, and therefore, use of this interface is optional.
Clock device register changes are normally made upon system
initialization, if any are required. The interface cannot be used during
system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write, and block read operations from the controller. For block
write/read operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the ability
to stop after any complete byte has been transferred. For byte write
and byte read operations, the system controller can access
individually indexed bytes. The offset of the indexed byte is encoded
in the command code, as described in
Table 3A.
The block write and block read protocol is outlined in
Table 3B,
while
Table 3C
outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
7
6:5
4:0
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Chip select address, set to “00” to access device.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Description = Block Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
©2016 Integrated Device Technology, Inc.
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Revision C, July 15, 2016
841S04 Datasheet
Table 3C. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29
Description = Byte Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Data Byte- 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
Control Registers
Table 4A. Byte 0: Control Register 0
Bit
7
6
@Pup
0
1
Name
Reserved
SRC[T/C]4
Description
Reserved
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z)
1 = Enable
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
1
1
1
0
1
0
1
0
SRCT/C
Reserved
Reserved
Reserved
Reserved
SRC
Reserved
Reserved
Table 4B. Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
1
SRC[T/C]3
4
1
SRC[T/C]2
3
2
1
0
1
1
0
0
SRC[T/C]1
Reserved
Reserved
Reserved
Table 4C. Byte 2: Control Register 2
Bit
@Pup
Name
Description
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
Reserved
Reserved
Reserved
Reserved
SRC Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
Reserved
Reserved
NOTE: Pup denotes Power-up.
©2016 Integrated Device Technology, Inc.
4
Revision C, July 15, 2016
841S04 Datasheet
Table 4D. Byte 3:Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
1
0
1
0
1
1
1
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 4G. Byte 6: Control Register 6
Bit
7
@Pup
0
Name
TEST_SEL
Description
REF/N or Hi-Z Select
0 = Hi-Z,
1 = REF/N
TEST Clock
Mode Entry Control
0 = Normal Operation,
1 = REF/N or Hi-Z Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
0
TEST_MODE
5
4
3
2
1
0
0
1
0
0
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NOTE: Pup denotes Power-up.
Table 4E. Byte 4: Control Register 4
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 4H. Byte 7: Control Register 7
Bit
7
6
5
4
3
2
1
@Pup
0
0
0
0
0
0
0
1
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Table 4F. Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
©2016 Integrated Device Technology, Inc.
5
Revision C, July 15, 2016
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