FemtoClock
®
Crystal-to-LVDS
Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
844031-01
DATA SHEET
G
ENERAL
D
ESCRIPTION
The 844031-01 is an Ethernet Clock Generator. The 844031-01
uses an 18pF parallel resonant crystal over the range of 19.6MHz
- 27.2MHz. For Ethernet applications, a 25MHz crystal is used to
generate 312.5MHz. The 844031-01 has excellent <1ps phase jitter
performance, over the 1.875MHz - 20MHz integration range. The
844031-01 is packaged in a small 8-pin TSSOP, making it ideal for
use in systems with limited board space.
F
EATURES
•
One differential LVDS output
•
Crystal oscillator interface, 18pF parallel resonant crystal
(19.6MHz - 27.2MHz)
•
Output frequency range: 245MHz - 340MHz
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.53ps (typical)
•
3.3V or 2.5V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
For functional replacement part use 8T49N242
C
OMMON
C
ONFIGURATION
T
ABLE
Inputs
Crystal Frequency (MHz)
25
M
25
N
2
Multiplication
Value M/N
12.5
Output Frequency
(MHz)
312.5
B
LOCK
D
IAGRAM
OE
Pullup
P
IN
A
SSIGNMENT
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷2
(fixed)
Q
nQ
844031-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷25
(fixed)
844031-01 REVISION A 6/2/16
1
©2016 Integrated Device Technology, Inc.
844031-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT, XTAL_IN
OE
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ output is active.
When LOW, the Q/nQ output is in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATORY
2
REVISION A 6/2/16
844031-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
10mA
15mA
129.5°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
Typical
3.3
3.3
Maximum
3.465
V
DD
75
10
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.10
Typical
2.5
2.5
Maximum
2.625
V
DD
70
10
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Parameter
Differential Output Voltage
OD
Test Conditions
Minimum
275
1.15
Typical
Maximum
425
50
Units
mV
mV
V
mV
Δ
V
V
OS
V
OD
Magnitude Change
Offset Voltage
1.33
V
OS
Magnitude Change
1.45
50
Δ
V
OS
NOTE: Please refer to Parameter Measurement Information for output information.
REVISION A 6/2/16
3
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
844031-01 DATA SHEET
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Parameter
Differential Output Voltage
OD
Test Conditions
Minimum
215
1.05
Typical
Maximum
430
50
Units
mV
mV
V
mV
Δ
V
V
OS
V
OD
Magnitude Change
Offset Voltage
1.26
V
OS
Magnitude Change
1.45
50
Δ
V
OS
NOTE: Please refer to Parameter Measurement Information for output information.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: It is not recommended to overdrive the crystal input with an external clock.
19.6
Test Conditions
Minimum
Typical
Fundamental
27.2
50
7
MHz
Ω
pF
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
312.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
200
48
Test Conditions
Minimum
245
0.53
400
52
Typical
Maximum
340
Units
MHz
ps
ps
%
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
312.5MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
200
48
Test Conditions
Minimum
245
0.68
400
52
Typical
Maximum
340
Units
MHz
ps
ps
%
NOTE 1: Please refer to the Phase Noise Plots following this section.
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATORY
4
REVISION A 6/2/16
844031-01 DATA SHEET
T
YPICAL
P
HASE
N
OISE AT
312.5MH
Z
@ 3.3V
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.53ps (typical)
➤
Ethernet Filter
312.5MHz
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
312.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.68ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
312.5MH
Z
@ 2.5V
➤
Ethernet Filter
➤
Phase Noise Result by adding
an Ethernet Filter to raw data
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
REVISION A 6/2/16
5
➤
Phase Noise Result by adding
an Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
DSP 与 ARM 处理器
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