Low Skew, 1-to-10 Differential-to-3.3V,
2.5V LVPECL/ECL Fanout Buffer
85310I-01
DATA SHEET
General Description
The 85310I-01 is a low skew, high performance 1-to-10
Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer. The CLKx,
nCLKx pairs can accept most standard differential input levels. The
85310I-01 is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 85310I-01 ideal for those clock distribution
applications demanding well defined performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Ten differential 2.5V, 3.3V LVPECL/ECL output pair
Two selectable differential input pairs
Differential CLKx/nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any single ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
Output skew: 30ps (typical)
Part-to-part skew: 140ps (typical)
Propagation delay: 2ns (typical)
Additive phase jitter, RMS: <0.13ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free RoHS compliant package
Block Diagram
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
Pin Assignment
V
CCO
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
V
CC
CLK_SEL
CLK0
nCLK0
nc
CLK1
nCLK1
V
EE
1
2
3
4
5
6
7
8
nQ0
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9
V
CCO
V
CCO
nQ1
Q0
Q1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
CLK_SEL
Pulldown
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
10 11 12 13 14 15 16
V
CCO
nQ7
nQ9
nQ8
Q9
Q8
Q7
85310I-01
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
85310I-01 Rev I 7/8/15
1
©2015 Integrated Device Technology, Inc.
85310I-01 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
CC
CLK_SEL
CLK0
nCLK0
nc
CLK1
nCLK1
V
EE
V
CCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Unused
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Type
Description
Positive supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
No connect.
Non-inverting differential clock input.
Inverting differential clock input.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
2
Rev I 7/8/15
85310I-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
3.3
3.3
Maximum
3.8
3.8
120
Units
V
V
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL
CLK_SEL
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Rev I 7/8/15
3
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
85310I-01 DATA SHEET
Table 3C. DC Characteristics,
V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
CLK[0:1],
Input High Current
nCLK[0:1]
CLK[0:1]
I
IL
Input Low Current
nCLK[0:1]
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Range; NOTE 1, 2
Test Conditions
V
CC
= V
IN
= 3.8V or 2.625V
V
CC
= V
IN
= 3.8V or 2.625V
V
CC
= 3.8V or 2.625V,
V
IN
= 0V
V
CC
= 3.8V or 2.625V,
V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
Table 3D. LVPECL DC Characteristics,
V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
swing
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.0
0.6
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CCO
– 2V.
AC Electrical Characteristics
Table 4. AC Characteristics,
V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
tjit
t
PD
tsk(pp)
tsk(o)
t
R
/ t
F
odc
Parameter
Output Frequency
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter section
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
47
<0.13
2
140
30
2.5
340
55
700
53
Test Conditions
Minimum
Typical
Maximum
700
Units
MHz
ps
ns
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
4
Rev I 7/8/15
85310I-01 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Rev I 7/8/15
5
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL
FANOUT BUFFER
stm32/stm8
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