74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Rev. 11 — 16 January 2013
Product data sheet
1. General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring
separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state
outputs for bus-oriented applications. It consists of two sections of eight positive
edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for
each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin
nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE
does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed 3.3 V and
5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC16374ADL
74LVCH16374ADL
74LVC16374ADGG
74LVCH16374ADGG
74LVC16374ABX
74LVCH16374ABX
40 C
to +125
C
40 C
to +125
C
TSSOP48
40 C
to +125
C
Name
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Type number
HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1
package; no leads; 60 terminals; UTLP based;
body 4
6
0.5 mm
4. Functional diagram
1
1OE
48
1CP
24
2OE
25
2CP
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1CP
48
2CP
25
001aaa253
EN1
C3
EN2
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
001aaa254
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
24
2OE
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 16 January 2013
2 of 20
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
1D0
D
CP
FF1
Q
1Q0
2D0
D
CP
FF2
Q
2Q0
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
001aaa255
Fig 3.
Logic diagram
V
CC
data input
to internal circuit
mna705
Fig 4.
Bus hold circuit
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 16 January 2013
3 of 20
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
74LVC16374A
74LVCH16374A
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48
1CP
47
1D0
46
1D1
45
GND
44
1D2
43
1D3
42
V
CC
41
1D4
40
1D5
39
GND
38
1D6
37
1D7
36
2D0
35
2D1
34
GND
33
2D2
32
2D3
31
V
CC
30
2D4
29
2D5
28
GND
27
2D6
26
2D7
25
2CP
001aaa231
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
2Q2
16
2Q3
17
V
CC
18
2Q4
19
2Q5
20
GND
21
2Q6
22
2Q7
23
2OE
24
Fig 5.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 16 January 2013
4 of 20
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
terminal 1
index area
74LVC16374A
74LVCH16374A
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B13
B14
B15
B16
B17
A25
A24
A23
A22
A21
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aaj618
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input.
Fig 6.
Pin configuration SOT1134-1 (HXQFN60U)
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 16 January 2013
5 of 20
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