NB3N106K
3.3V Differential 1:6 Fanout
Clock Driver with HCSL
Outputs
Description
The NB3N106K is a differential 1:6 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N106K is designed
with HCSL PCI Express clock distribution and FBDIMM
applications in mind.
Inputs can directly accept differential LVPECL, LVDS, and HCSL
signals per Figures 7, 8, and 9. Single−ended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external V
th
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50
W
termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475
W
resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N106K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N106K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
http://onsemi.com
QFN−24
MN SUFFIX
CASE 485L
MARKING DIAGRAM*
NB3N
106K
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333, and
•
•
•
•
•
•
•
•
•
•
•
•
400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd
100 ps Maximum Propagation Delay Variation per Diff Pair
0.1 ps Typical Integrated Phase Jitter RMS
Operating Range: V
CC
=
3.0 V to 3.6 V with V
EE
=
0 V
Typical HCSL Output Levels (700 mV Peak−to−Peak)
LVDS Output Levels with Interface Termination
These are Pb−Free Devices*
Clock Distribution
PCIe, II, III
Networking and Communications
High End Computing
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
CLK
CLK
Q1
Applications
Q4
Q4
VTCLK
V
CC
GND
IREF
R
REF
Q5
Q5
End Products
•
Servers
•
FBDIMM Memory Cards
•
Ethernet Switch/Routers
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
April, 2012
−
Rev. 5
1
Publication Order Number:
NB3N106K/D
NB3N106K
Exposed Pad (EP)
VCC
VCC
19
18
17
16
VCC
Q2
Q2
Q3
Q3
VCC
Q1
21
Q0
Q0
Q1
20
24
IREF
VTCLK
CLK
CLK
VTCLK
GND
1
2
3
23
22
NB3N106K
4
5
6
7
VCC
8
Q5
9
Q5
10
Q4
11
Q4
12
VCC
15
14
13
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
1
Name
IREF
I/O
Description
Use the IREF pin to set the output drive. Connect a 475
W
RREF resistor from the
IREF pin to GND to produce 2.6 mA of IREF current. A current mirror multiplies
IREF by a factor of 5.4x to force 14 mA through a 50
W
output load. See Figures 6
and 12.
−
Internal 50
W
Termination Resistor connection Pins. In the differential configuration
when the input termination pins are connected to the common termination voltage,
and if no signal is applied then the device may be susceptible to self−oscillation.
Clock (TRUE) Input
2, 5
VTCLK,
VTCLK
CLK
3
LVPECL,
HCSL, LVDS
Input
LVPECL,
HCSL, LVDS
Input
HCSL or
LVDS (Note 1)
Output
HCSL or
LVDS
(Note 1)
Output
−
−
GND
4
CLK
Clock (INVERT) Input
8, 10, 14, 16, 20,
22
9, 11, 15, 17, 21,
23
Q[5−0]
Output (INVERT) (Note 1)
Q[5−0]
Output (TRUE) (Note 1)
6
7, 12, 13, 18, 19,
24
Exposed Pad
GND
V
CC
EP
Supply Ground. GND pin must be externally connected to power supply to
guarantee proper operation.
Positive Voltage Supply pin. V
CC
pin must be externally connected to a power
supply to guarantee proper operation.
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a sufficient heat−sinking conduit for proper thermal
operation and electrically connected to the circuit board ground (GND).
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
http://onsemi.com
2
NB3N106K
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN−24
Oxygen Index: 28 to 34
Value
>2 kV
200 V
Level 1
UL 94 V−0 @ 0.125 in
286
Table 3. MAXIMUM RATINGS
(Note 3)
Symbol
V
CC
V
I
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 3)
QFN−24
QFN−24
QFN−24
Condition 1
GND = 0 V
GND = 0 V
Continuous
Surge
QFN−24
Condition 2
Rating
4.6
GND
−
0.3
≤
V
I
≤
V
CC
50
100
−40
to +85
−65
to +150
37
32
11
265
Unit
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 51−6, multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad..
http://onsemi.com
3
NB3N106K
Table 4. DC CHARACTERISTICS
(V
CC
= 3.0 V to 3.6 V, T
A
=
−40°C
to +85°C Note 4)
Symbol
I
GND
I
CC
I
IH
I
IL
R
TIN
V
th
V
IH
V
IL
V
IHD
V
ILD
V
ID
V
CMR
V
OH
V
OL
Characteristic
GND Supply Current (All Outputs Loaded)
Power Supply Current (All Outputs Loaded)
Input HIGH Current
Input LOW Current
Internal Input Termination Resistor
−150
45
Min
Typ
60
210
2.0
−2.0
50
55
Max
90
260
150
Unit
mA
mA
mA
mA
W
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
Input Threshold Reference Voltage Range (Note 5)
Single*Ended Input HIGH Voltage
Single*Ended Input LOW Voltage
350
V
th
+ 150
GND
V
CC
−
1000
V
CC
V
th
−
150
V
CC
−
850
V
CC
−
1000
V
CC
−
850
V
CC
−
1000
740
0
900
150
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 7, 8 and 9)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
*
V
ILD
)
Input Common Mode Range
425
GND
150
350
mV
mV
mV
mV
HCSL OUTPUTS
(Figure 4)
Output HIGH Voltage
Output LOW Voltage
600
−150
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurements taken with with outputs loaded 50
W
to GND. Connect a 475
W
resistor from IREF (Pin 1) to GND. See Figure 6.
5. V
th
is applied to the complementary input when operating in single ended mode per Figure 4.
http://onsemi.com
4
NB3N106K
Table 5. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V;
−40°C
to +85°C (Note 6)
Symbol
V
OUTPP
t
PLH
,
t
PHL
Dt
PLH
,
Dt
PHL
t
SKEW
Characteristic
Output Voltage Amplitude (@ V
INPPmin
) f
in
≤
400 MHz
Propagation Delay (See Figure 3a)
CLK/CLK to Qx/Qx
550
Min
Typ
725
800
Max
1000
1100
Unit
mV
ps
ps
ps
Propagation Delay Variation Per Each Diff Pair (Note 7) (See Figure 3a)
CLK/CLK to Qx/Qx
Duty Cycle Skew (Note 8)
Within -Device Skew
Device to Device Skew (Note 9)
Integrated Phase Jitter RMS (Note 10)
Input Voltage Swing/Sensitivity
(Differential Configuration)
Absolute Crossing Magnitude Voltage (See Figure 3b)
Variation in Magnitude of V
CROSS
(See Figure 3b)
Absolute Magnitude in Output Risetime and Falltime (from 175 mV to 525 mV)
(See Figure 3b)
Qx, Qx
150
220
0.150
250
0.1
100
20
100
150
t
JIT
q
V
INPP
V
CROSS
DV
CROSS
t
r
, t
f
Dtr, Dtf
ps
V
CC
−
0.85
550
150
400
125
V
mV
mV
ps
ps
Variation in Magnitude of Risetime and Falltime (Single−Ended) at V
CC
= 3.0 V, 3.3 V,
3.6 V (See Figure 3b)
Qx, Qx
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. Measurements taken all outputs loaded 50
W
to GND per Figure 6.
Connect a 475
W
resistor from IREF (Pin 1) to GND. See Figure 6.
7. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges per Figure 3.
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw-
and T
pw+
.
9. Skew is measured between outputs under identical transition conditions @ 50 MHz.
10. Phase noise integrated from 12 kHz to 20 MHz.
http://onsemi.com
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
