FM24CL64B
64-Kbit (8K × 8) Serial (I
2
C) F-RAM
64-Kbit (8K × 8) Serial (I
2
C) F-RAM
Features
■
Functional Description
The FM24CL64B is a 64-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24CL64B performs write operations at
bus speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The
FM24CL64B is capable of supporting 10
14
read/write cycles, or
100 million times more write cycles than EEPROM.
These capabilities make the FM24CL64B ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24CL64B provides substantial benefits to users of serial
(I
2
C) EEPROM as a hardware drop-in replacement. The device
specifications are guaranteed over an industrial temperature
range of –40
C
to +85
C.
For a complete list of related documentation, click
here.
64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8K × 8
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (See the
Data Retention and
Endurance
table)
❐
NoDelay™ writes
❐
Advanced high-reliability ferroelectric process
Fast 2-wire Serial interface (I
2
C)
❐
Up to 1-MHz frequency
2
❐
Direct hardware replacement for serial (I C) EEPROM
❐
Supports legacy timings for 100 kHz and 400 kHz
Low power consumption
❐
100
A
(typ) active current at 100 kHz
❐
3
A
(typ) standby current
Voltage operation: V
DD
= 2.7 V to 3.65 V
Industrial temperature: –40
C
to +85
C
Packages
❐
8-pin small outline integrated circuit (SOIC) package
❐
8-pin thin dual flat no leads (DFN) package
Restriction of hazardous substances (RoHS) compliant
■
■
■
■
■
■
Logic Block Diagram
Counter
Address
Latch
13
8Kx8
F-RAM Array
8
SDA
Serial to Parallel
Converter
Data Latch
8
SCL
WP
A2-A0
Control Logic
Cypress Semiconductor Corporation
Document Number: 001-84458 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 20, 2017
FM24CL64B
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
I2C Interface ...................................................................... 4
STOP Condition (P) ..................................................... 4
START Condition (S) ................................................... 4
Data/Address Transfer ................................................ 5
Acknowledge/No-acknowledge ................................... 5
Slave Device Address ................................................. 6
Addressing Overview .................................................. 6
Data Transfer .............................................................. 6
Memory Operation ............................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Endurance ......................................................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
Power Cycle Timing ....................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 001-84458 Rev. *I
Page 2 of 18
FM24CL64B
Pinouts
Figure 1. 8-pin SOIC pinout
A0
1
2
3
4
Top View
not to scale
8
7
6
5
VDD
WP
SCL
SDA
A1
A2
VSS
Figure 2. 8-pin DFN pinout
O
A0
A1
A2
VSS
1
2
EXPOSED
PAD
3
4
8
7
6
5
VDD
WP
SCL
SDA
Top View
not to scale
Pin Definitions
Pin Name
A2–A0
I/O Type
Input
Description
Device Select Address 2–0.
These pins are used to select one of up to 8 devices of the same type
on the same I
2
C bus. To select the device, the address value on the three pins must match the
corresponding bits contained in the slave address. The address pins are pulled down internally.
SDA
Input/Output
Serial Data/Address.
This is a bi-directional pin for the I
2
C interface. It is open-drain and is intended
to be wire-AND'd with other devices on the I
2
C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
Input
Serial Clock.
The serial clock pin for the I
2
C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
Write Protect.
When tied to V
DD
, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
SCL
WP
V
SS
V
DD
EXPOSED
PAD
Input
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect
The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The EXPOSED
PAD should not be soldered on the PCB.
Document Number: 001-84458 Rev. *I
Page 3 of 18
FM24CL64B
Functional Overview
The FM24CL64B is a serial F-RAM memory. The memory array
is logically organized as 8,192 × 8 bits and is accessed using an
industry-standard I
2
C interface. The functional operation of the
F-RAM is similar to serial (I
2
C) EEPROM. The major difference
between the FM24CL64B and a serial (I
2
C) EEPROM with the
same pinout is the F-RAM’s superior write performance, high
endurance, and low power consumption.
a new bus transaction can be shifted into the device, a write
operation is complete. This is explained in more detail in the
interface section.
I
2
C Interface
The FM24CL64B employs a bi-directional I
2
C bus protocol using
few pins or board space.
Figure 3
illustrates a typical system
configuration using the FM24CL64B in a microcontroller-based
system. The industry standard I
2
C bus is familiar to many users
but is described in this section.
By convention, any device that is sending data onto the bus is
the transmitter while the target device for this data is the receiver.
The device that is controlling the bus is the master. The master
is responsible for generating the clock signal for all operations.
Any device on the bus that is being controlled is a slave. The
FM24CL64B is always a slave device.
The bus protocol is controlled by transition states in the SDA and
SCL signals. There are four conditions including START, STOP,
data bit, or acknowledge.
Figure 4 on page 5
and
Figure 5 on
page 5
illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the electrical
specifications section.
Memory Architecture
When accessing the FM24CL64B, the user addresses 8K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the I
2
C
protocol, which includes a slave address (to distinguish other
non-memory devices) and a two-byte address. The upper 3 bits
of the address range are 'don't care' values. The complete
address of 13 bits specifies each byte address uniquely.
The access time for the memory operation is essentially zero,
beyond the time needed for the serial protocol. That is, the
memory is read or written at the speed of the I
2
C bus. Unlike a
serial (I
2
C) EEPROM, it is not necessary to poll the device for a
ready condition because writes occur at bus speed. By the time
Figure 3. System Configuration using Serial (I
2
C) nvSRAM
V DD
R
Pmin
= (V
DD
- V
OL
max) / I
OL
R
Pmax
= t
r
/ (0.8473 * C
b
)
SDA
Microcontroller
SCL
V DD
V DD
A0
A1
A2
SCL
SDA
WP
A0
A1
A2
SCL
SDA
WP
A0
A1
A2
SCL
SDA
WP
#0
#1
#7
STOP Condition (P)
A STOP condition is indicated when the bus master drives SDA
from LOW to HIGH while the SCL signal is HIGH. All operations
using the FM24CL64B should end with a STOP condition. If an
operation is in progress when a STOP is asserted, the operation
will be aborted. The master must have control of SDA in order to
assert a STOP condition.
START Condition (S)
A START condition is indicated when the bus master drives SDA
from HIGH to LOW while the SCL signal is HIGH. All commands
should be preceded by a START condition. An operation in
progress can be aborted by asserting a START condition at any
time. Aborting an operation using the START condition will ready
the FM24CL64B for a new operation.
If during operation the power supply drops below the specified
V
DD
minimum, the system should issue a START condition prior
to performing another operation.
Document Number: 001-84458 Rev. *I
Page 4 of 18
FM24CL64B
Figure 4. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
S
START Condition
P
STOP Condition
SCL
Figure 5. Data Transfer on the I
2
C Bus
handbook, full pagewidth
P
S
SDA
MSB
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
SCL
S
START
condition
1
2
7
8
9
ACK
1
2
3
4-8
9
ACK
S
or
P
STOP or
START
condition
Byte complete
Data/Address Transfer
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should not change while SCL is HIGH.
The receiver would fail to acknowledge for two distinct reasons.
First is that a byte transfer fails. In this case, the no-acknowledge
ceases the current operation so that the device can be
addressed again. This allows the last byte to be recovered in the
event of a communication error.
Second and most common, the receiver does not acknowledge
to deliberately end an operation. For example, during a read
operation, the FM24CL64B will continue to place data onto the
bus as long as the receiver sends acknowledges (and clocks).
When a read operation is complete and no more data is needed,
the receiver must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the FM24CL64B to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.
Acknowledge/No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does not drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted.
Figure 6. Acknowledge on the I
2
C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
No Acknowledge
DATA OUTPUT
BY SLAVE
Acknowledge
SCL FROM
MASTER
S
START
Condition
Clock pulse for
acknowledgement
1
2
8
9
Document Number: 001-84458 Rev. *I
Page 5 of 18
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