CY29942
1:18 Clock Distribution Buffer
1:18 Clock Distribution Buffer
Features
Functional Description
The CY29942 is a low voltage clock distribution buffer with an
LVCMOS or LVTTL compatible clock input. The output enable
control input is LVCMOS/LVTTL compatible. The eighteen
outputs are 2.5 V or 3.3 V LVCMOS or LVTTL compatible,
operate up to 200 MHz, and can drive 50
series
or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces,
giving the devices an effective fanout of 1:36. Low
output-to-output skews make the CY29942 an ideal clock
distribution buffer for nested clock trees in the most demanding
of synchronous systems.
For a complete list of related documentation,
click here.
Operational range: Up to 200 MHz
LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible logic input
18 clock outputs: Drive up to 36 clock lines
Output-to-output Skew: 110 ps (typical)
Output enable control
Supply voltage: 2.5 V or 3.3 V
Temperature range: Commercial and Industrial
32-pin TQFP package
Pin compatible with MPC942C
Logic Block Diagram
VDD
TCLK
OE
18
Q0-Q17
Cypress Semiconductor Corporation
Document Number: 38-07284 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 21, 2017
CY29942
Pin Configuration
Figure 1. 32-pin TQFP pinout
VDD
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
VSS
TCLK
NC
OE
NC
VDD
VDD
1
2
3
4
5
6
7
8
9
VSS
Q0
Q1
Q2
Q3
Q4
Q5
CY29942
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
10
11
12
13
14
Q13
15
Q12
Pin Descriptions
Pin
3
5
9, 10, 11, 13,
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
7, 8, 16, 21,
29
1, 2, 12, 17,
25
4, 6
Name
TCLK
OE
Q(17:0)
I/O
Input
Input
Output
Description
External reference/Test clock input. Weak internal pull-down resistor.
Output enable. When HIGH, all outputs are enabled. When set LOW, the outputs are
at high impedance. Weak internal pull-up resistor.
Clock outputs
VDD
VSS
NC
2.5 V or 3.3 V power supply
Ground
No connection
Document Number: 38-07284 Rev. *L
VDD
Q17
Q16
Q15
VSS
Q14
16
Page 2 of 10
CY29942
Absolute Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
[1]
Maximum input voltage relative to V
SS
: ............. V
SS
– 0.3 V
Maximum input voltage relative to V
DD
: ............. V
DD
+ 0.3 V
Storage temperature: ................................. –65 °C to 150 °C
Operating temperature: ............................... –40 °C to 85 °C
Maximum ESD protection .............................................. 2 kV
Maximum power supply: ............................................... 5.5 V
Maximum input current: ............................................ ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, I/O voltages should be constrained to the range:
V
SS
< V
I/O
< V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Electrical Specifications
V
DD
= 3.3 V ± 5% or 2.5 V ± 5% over the specified temperature range.
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DDQ
I
DD
Description
Input low voltage
Input high voltage
Input low current
[2]
Input high current
[2]
Output low voltage
[3]
Output high voltage
[3]
Quiescent supply current
Dynamic supply current
I
OL
= 20 mA
I
OH
= –20 mA, V
DD
= 3.3 V
I
OH
= –16 mA, V
DD
= 2.5 V
OE = V
SS
V
DD
= 3.3 V, Outputs at 150 MHz,
CL = 15 pF
V
DD
= 3.3 V, Outputs at 200 MHz,
CL = 15 pF
V
DD
= 2.5 V, Outputs at 150 MHz,
CL = 15 pF
V
DD
= 2.5 V, Outputs at 200 MHz,
CL = 15 pF
Z
out
C
in
Output impedance
Input capacitance
V
DD
= 3.3 V
V
DD
= 2.5 V
Conditions
Min
V
SS
2.0
–
–
–
2.4
2.0
–
–
–
–
–
8
10
–
Typ
–
–
–
–
–
–
–
5
285
335
200
240
12
15
4
Max
0.8
V
DD
–200
200
0.5
–
–
7
–
–
–
–
16
20
–
Unit
V
V
µA
µA
V
V
V
mA
mA
mA
mA
mA
pF
Thermal Resistance
Parameter
[4]
θ
JA
θ
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
32-pin TQFP
67
28
Unit
°C/W
°C/W
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Inputs have pull-up/pull-down resistors that effect input current.
3. Driving series or parallel terminated 50 (or 50
to V
DD
/2) transmission lines.
4. These parameters are guaranteed by design and are not tested.
Document Number: 38-07284 Rev. *L
Page 3 of 10
CY29942
AC Electrical Specifications
V
DD
= 3.3 V ±5% or 2.5 V ±5% over the specified temperature range
[5]
Parameter
Fmax
tpd
DC
tsk(0)
tskew(pp)
tskew(pp)
tr/tf
Description
Input frequency
TTL_CLK to Q delay
[6, 7]
Output duty
cycle
[6, 7, 8]
V
DD
= 3.3 V
V
DD
= 2.5 V
Measured at V
DD
/2
V
DD
= 3.3 V
V
DD
= 2.5 V
Part-to-part skew
[10]
Output clocks rise/fall time
[6, 7]
0.8 V to 2.0 V, V
DD
= 3.3 V;
0.5 V to 1.8 V, V
DD
= 2.5 V
Output-to-output skew
[6, 7]
Part-to-part skew
[9]
Conditions
Min
–
1.8
2.3
45
–
–
–
–
0.2
Typ
–
3.3
3.8
–
110
–
–
–
–
Max
200
3.8
4.4
55
200
1.0
1.3
600
1.1
Unit
MHz
ns
ns
%
ps
ns
ns
ps
ns
Notes
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50
transmission lines.
7. See
Figure 2.
8. 50% input duty cycle.
9. Across temperature and voltage ranges, includes output skew.
10. For a specific temperature and voltage, includes output skew.
Document Number: 38-07284 Rev. *L
Page 4 of 10
CY29942
Figure 2. LVCMOS_CLK CY29942 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
CY29942 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
VTT
Figure 3. LVCMOS Propagation Delay (tpd) Test Reference
LVCMOS_CLK
VTT
VCC
VCC /2
GND
VCC
Q
VCC /2
t
PD
Figure 4. Output Duty Cycle (DC)
GND
VCC
t
P
T0
VCC /2
GND
DC = tP / T0 x 100%
Figure 5. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
t
SK(0)
GND
Document Number: 38-07284 Rev. *L
Page 5 of 10
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