74ACT161MTR: 产品描述Counter Shift Registers 4-Bit Binary Counter; 产品类别逻辑逻辑; 文件大小332KB，共13页; 制造商ST(意法半导体); 官网地址http://www.st.com/; 标准

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74ACT161MTR概述

Counter Shift Registers 4-Bit Binary Counter

74ACT161MTR规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	ST(意法半导体)
零件包装代码	SOIC
包装说明	SOP, SOP16,.25
针数	16
Reach Compliance Code	compliant
计数方向	UP
系列	ACT
JESD-30 代码	R-PDSO-G16
JESD-609代码	e4
长度	9.9 mm
负载电容（CL）	50 pF
负载/预设输入	YES
逻辑集成电路类型	BINARY COUNTER
最大频率@ Nom-Sup	85000000 Hz
最大I（ol）	0.024 A
工作模式	SYNCHRONOUS
湿度敏感等级	1
位数	4
功能数量	1
端子数量	16
最高工作温度	125 °C
最低工作温度	-55 °C
封装主体材料	PLASTIC/EPOXY
封装代码	SOP
封装等效代码	SOP16,.25
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE
包装方法	TAPE AND REEL
峰值回流温度（摄氏度）	260
电源	5 V
传播延迟（tpd）	10.5 ns
认证状态	Not Qualified
座面最大高度	1.75 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
触发器类型	POSITIVE EDGE
宽度	3.9 mm
最小 fmax	85 MHz
Base Number Matches	1

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74ACT161

SYNCHRONOUS PRESETTABLE 4-BIT COUNTER

HIGH SPEED:

MAX

= 290MHz (TYP.) at V

= 5V

LOW POWER DISSIPATION:

= 8µA(MAX.) at T

=25°C

COMPATIBLE WITH TTL OUTPUTS

= 2V (MIN.), V

= 0.8V (MAX.)

50Ω TRANSMISSION LINE DRIVING

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

| = I

= 24mA (MIN)

BALANCED PROPAGATION DELAYS:

PLH

≅

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 4.5V to 5.5V

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 161

IMPROVED LATCH-UP IMMUNITY

DIP

SOP

TSSOP

ORDER CODES

PACKAGE

DIP

SOP

TSSOP

TUBE

74ACT161B

74ACT161M

T&R

74ACT161MTR

74ACT161TTR

DESCRIPTION

The 74ACT161 is an advanced high-speed CMOS

SYNCRONOUS PRESETTABLE COUNTER

fabricated with sub-micron silicon gate and

double-layer metal wiring C

MOS tecnology. It is a

4 bit binary counter with Asynchronous Clear.

The circuit have four fundamental modes of

operation, in order of preference: synchronous

reset, parallel load, count-up and hold. Four

control inputs, (CLEAR), (LOAD), (PE) and (TE),

determine the mode of operation as shown in the

Truth Table. A LOW signal on CLEAR overrides

counting and parallel loading and sets all outputs

on LOW state. A LOW signal on LOAD overrides

PIN CONNECTION AND IEC LOGIC SYMBOLS

counting and allows information on Parallel Data

inputs to be loaded into the flip-flop on the next

rising edge of CLOCK. With LOAD and CLEAR

HIGH, PE and TE permit counting when both are

HIGH. Conversely, a LOW signal on either PE and

TE inhibits counting.

The CARRY OUTPUT is HIGH when TE is HIGH

and counter is in state 15.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

April 2001

1/13

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