1-to-2, LVCMOS/LVTTL- To- Differential
HSTL Translator
General Description
The ICS85222I-02 is a 1-to-2 LVCMOS / LVTTL-to- Differential HSTL
translator. The ICS85222I-02 has one single-ended clock input. The
single-ended clock input accepts LVCMOS or LVTTL input levels and
translates them to HSTL levels. The small outline 8-pin SOIC
package makes this device ideal for applications where space, high
performance and low power are important.
ICS85222I-02
DATASHEET
Features
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Two differential HSTL outputs
One LVCMOS/LVTTL clock input
CLK input can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
Part-to-part skew: 500ps (maximum)
Propagation delay: 1.55ns (maximum)
V
OH
: 1.4V (maximum)
Output crossover voltage: 0.5V - 0.9V
Full 3.3V operating supply voltage
-40°C to 85°C ambient operating temperature
Lead-free RoHS compliant packaging
Block Diagram
Q0
nQ0
Q1
nQ1
Pin Assignment
Q0
1
2
3
4
8
V
DD
CLK
Pulldown
Q1
nQ1
5
GND
ICS85222I-02
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
ICS85222AMI-02 APRIL 25, 2014
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©2014 Integrated Device Technology, Inc.
ICS85222I-02 Data Sheet
1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
Q0
nQ0
Q1
nQ1
GND
nc
CLK
V
DD
Output
Output
Output
Output
Power
Unused
Input
Power
Pulldown
Type
Description
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
No connect
LVCMOS / LVTTL clock input.
Positive supply pin.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
NOTE: Unused output pairs must be terminated.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
ICS85222AMI-02 APRIL 25, 2014
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©2014 Integrated Device Technology, Inc.
ICS85222I-02 Data Sheet
1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Junction Temperature, T
J
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
125°C
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Outputs not loaded
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 3C. HSTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
1.0
0
0.5
0.6
1.0
Typical
Maximum
1.4
0.4
0.9
1.4
Units
V
V
V
V
NOTE 1: All outputs must be terminated with 50 to ground.
ICS85222AMI-02 APRIL 25, 2014
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©2014 Integrated Device Technology, Inc.
ICS85222I-02 Data Sheet
1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
AC Electrical Characteristics
Table 4. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
tsk(o)
tsk(pp)
t
R
/t
F
odc
Symbol
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ
250MHz
ƒ
250MHz
225
40
35
ƒ
350MHz
1.0
Test Conditions
Minimum
Typical
Maximum
350
1.55
35
500
700
60
65
Units
MHz
ns
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All outputs must be terminated with 50 to ground.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential crosspoints.
ICS85222AMI-02 APRIL 25, 2014
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©2014 Integrated Device Technology, Inc.
ICS85222I-02 Data Sheet
1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
Parameter Measurement Information
3.3V±5%
V
DD
Qx
SCOPE
Par t 1
nQx
Qx
HSTL
nQx
nQy
Qy
Par t 2
GND
tsk(pp)
0V
3.3V Core/3.3V Output Load AC Test Circuit
Part-to-Part Skew
nQx
V
DD
Qx
nQy
Qy
CLK
nQ0, nQ1
Q0, Q1
2
t
PD
Output Skew
Propagation Delay
nQ0,nQ1
Q0,Q1
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
ICS85222AMI-02 APRIL 25, 2014
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©2014 Integrated Device Technology, Inc.
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