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74AUP2G240GF115

产品描述Buffers u0026 Line Drivers Low-Power dual inverting buffer
产品类别半导体    逻辑   
文件大小892KB,共25页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
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74AUP2G240GF115概述

Buffers u0026 Line Drivers Low-Power dual inverting buffer

74AUP2G240GF115规格参数

参数名称属性值
产品种类
Product Category
Buffers & Line Drivers
制造商
Manufacturer
NXP(恩智浦)
RoHSDetails
系列
Packaging
Reel
工厂包装数量
Factory Pack Quantity
5000

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74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
Rev. 8 — 24 January 2013
Product data sheet
1. General description
The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The
3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE
causes the output to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input nOE is HIGH.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low-noise overshoot and undershoot < 10 % of V
CC
Input-disable feature allows floating input conditions
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C

74AUP2G240GF115相似产品对比

74AUP2G240GF115 74AUP2G240GM125 74AUP2G240DC125
描述 Buffers u0026 Line Drivers Low-Power dual inverting buffer Buffers u0026 Line Drivers 1.8V DUAL LOW-POW Buffers u0026 Line Drivers 1.8V DUAL LOW-POW
产品种类
Product Category
Buffers & Line Drivers Buffers & Line Drivers Buffers & Line Drivers
制造商
Manufacturer
NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
RoHS Details Details Details
系列
Packaging
Reel Reel Reel
工厂包装数量
Factory Pack Quantity
5000 4000 3000
Number of Input Lines - 2 Input 2 Input
Number of Output Lines - 2 Output 2 Output
Polarity - Inverting Inverting
电源电压-最大
Supply Voltage - Max
- 3.6 V 3.6 V
电源电压-最小
Supply Voltage - Min
- 0.8 V 0.8 V
最小工作温度
Minimum Operating Temperature
- - 40 C - 40 C
最大工作温度
Maximum Operating Temperature
- + 125 C + 125 C
安装风格
Mounting Style
- SMD/SMT SMD/SMT
封装 / 箱体
Package / Case
- XQFN8U-8 VSSOP-8
Function - Buffer/Line Driver Buffer/Line Driver
高度
Height
- 0.45 mm (Max) 0.85 mm (Max)
High Level Output Current - - 4 mA - 4 mA
Input Signal Type - Single-Ended Single-Ended
长度
Length
- 1.65 mm (Max) 2.1 mm (Max)
Logic Family - AUP AUP
Low Level Output Current - 4 mA 4 mA
Number of Channels - 2 2
工作电源电压
Operating Supply Voltage
- 1.8 V, 2.5 V, 3.3 V 1.8 V, 2.5 V, 3.3 V
输出类型
Output Type
- 3-State 3-State
传播延迟时间
Propagation Delay Time
- 21.6 ns at 1.1 V to 1.3 V, 12.3 ns at 1.4 V to 1.6 V, 9.5 ns at 1.65 V to 1.95 V, 7.1 ns at 2.3 V to 2.7 V, 6.4 ns at 3 V to 3.6 V 21.6 ns at 1.1 V to 1.3 V, 12.3 ns at 1.4 V to 1.6 V, 9.5 ns at 1.65 V to 1.95 V, 7.1 ns at 2.3 V to 2.7 V, 6.4 ns at 3 V to 3.6 V
Quiescent Current - 500 nA 500 nA
Supply Current - Max - 0.5 uA 0.5 uA
技术
Technology
- CMOS CMOS
宽度
Width
- 1.65 mm (Max) 2.4 mm (Max)

 
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