PTN3361C
Enhanced performance HDMI/DVI level shifter with active DDC
buffer, supporting 1.65 Gbit/s operation
Rev. 1.1 — 28 July 2015
Product data sheet
1. General description
PTN3361C is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain
current-steering differential output signals, up to 1.65 Gbit/s per lane to support 1080p
applications. Each of these lanes provides a level-shifting differential buffer to translate
from low-swing AC-coupled differential signaling on the source side, to TMDS-type
DC-coupled differential current-mode signaling terminated into 50
to 3.3 V on the sink
side. Additionally, PTN3361C provides a single-ended active buffer for voltage translation
of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a
channel with active buffering and level shifting of the DDC channel (consisting of a clock
and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is
implemented using active I
2
C-bus buffer technology providing capacitive isolation,
redriving and level shifting as well as disablement (isolation between source and sink) of
the clock and data lines.
The low-swing AC-coupled differential input signals to PTN3361C typically come from a
display source with multi-mode I/O, which supports multiple display standards, for
example, DisplayPort, HDMI and DVI. While the input differential signals are configured to
carry DVI or HDMI coded data, they do not comply with the electrical requirements of the
DVI v1.0 or HDMI v1.4b specification. By using PTN3361C, chip set vendors are able to
implement such reconfigurable I/Os on multi-mode display source devices, allowing the
support of multiple display standards while keeping the number of chip set I/O pins low.
See
Figure 1.
PTN3361C features low-swing self-biasing differential inputs which are compliant to the
electrical specifications of
DisplayPort Standard v1.2
and/or
PCI Express Standard v1.1,
and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b
electrical specifications. The I
2
C-bus channel actively buffers as well as level-translates
the DDC signals for optimal capacitive isolation. PTN3361C also supports power-saving
modes in order to minimize current consumption when no display is active or connected.
PTN3361C can be used for either HDMI or DVI level shifting. It provides additional
features supporting HDMI dongle detection; since support of HDMI dongle detection via
the DDC channel is mandatory, the system applications shall enable this feature for
correct operation.
PTN3361C is powered from a single 3.3 V power supply and is offered in a 32-terminal
HVQFN32 package.
NXP Semiconductors
PTN3361C
HDMI/DVI level shifter supporting 1.65 Gbit/s operation
MULTI-MODE DISPLAY SOURCE
OE_N
reconfigurable I/Os
PCIe PHY ELECTRICAL
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
coded
data
PCIe
output buffer
TX
FF
TX
TMDS
clock
pattern
PCIe
output buffer
TX
FF
TX
AC-coupled
differential pair
clock
CLOCK LANE
IN_D1+
IN_D1-
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D2+
IN_D2-
OUT_D2+
OUT_D2-
AC-coupled
differential pair
TMDS data
IN_D3+
DATA LANE
IN_D3-
OUT_D3+
OUT_D3-
AC-coupled
differential pair
TMDS data
IN_D4+
DATA LANE
IN_D4-
OUT_D4+
OUT_D4-
PTN3361C
OUT_D1+
OUT_D1-
DVI/HDMI
CONNECTOR
0 V to 3.3 V
quinary input
3.3 V
3.3 V
HPD_SOURCE
EQ3
DDC_EN
(0 V to 3.3 V)
HPD_SINK
0 V to 5 V
5V
SCL_SOURCE
3.3 V
DDC I/O
(I
2
C-bus)
CONFIGURATION
SDA_SOURCE
DDET
SCL_SINK
5V
SDA_SINK
aaa-014383
Remark:
TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3361C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 28 July 2015
2 of 30
NXP Semiconductors
PTN3361C
HDMI/DVI level shifter supporting 1.65 Gbit/s operation
2. Features and benefits
2.1 High-speed TMDS level shifting
Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.4b compliant open-drain current-steering differential output signals
TMDS level shifting operation up to 1.65 Gbit/s per lane
Programmable equalizer
Integrated 50
termination resistors for self-biasing differential inputs
Back-current safe outputs to disallow current when device power is off and monitor is
on
Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)
Rise time accelerator on sink-side DDC ports
0 Hz to 400 kHz I
2
C-bus clock frequency
Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting
HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or
from 5 V on the sink side to 3.3 V on the source side
Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 HDMI dongle detect support
Incorporates I2C slave ROM
Responds to DDC read to address 81h with predetermined byte sequence
Feature enabled by DDET pin (must be enabled for correct system operation using
HDMI dongle)
2.5 General
Power supply 3.0 V to 3.6 V
ESD resilience to 6 kV HBM, 1 kV CDM
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required
32-terminal HVQFN32 package
PTN3361C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 28 July 2015
3 of 30
NXP Semiconductors
PTN3361C
HDMI/DVI level shifter supporting 1.65 Gbit/s operation
3. Applications
PC motherboard/graphics card
Docking station
DisplayPort to HDMI dongles/adapters supporting deep color video formats (must
enable DDET)
DisplayPort to DVI dongles/adapters required to drive long cables
4. Ordering information
Table 1.
Ordering information
Topside mark
3361C
Package
Name
PTN3361CBS
HVQFN32
Description
plastic thermal enhanced very thin quad flat package; no
leads; 32 terminals; body 5 x 5 x 0.85 mm
Version
SOT617-3
Type number
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
Package
Packing method
Minimum
order
quantity
6000
Temperature range
Type number
PTN3361CBS
PTN3361CBSMP HVQFN32
Reel 13” Q2/T3
*standard mark SMD dry pack
T
amb
=
40 C
to +85
C
PTN3361C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 28 July 2015
4 of 30
NXP Semiconductors
PTN3361C
HDMI/DVI level shifter supporting 1.65 Gbit/s operation
5. Functional diagram
OE_N
input bias
enable
50 W
50 W
PTN3361C
OUT_D4+
OUT_D4-
IN_D4+
IN_D4-
input bias
EQ
enable
enable
50 W
50 W
OUT_D3+
OUT_D3-
IN_D3+
IN_D3-
input bias
EQ
enable
enable
50 W
50 W
OUT_D2+
OUT_D2-
IN_D2+
IN_D2-
input bias
EQ
enable
enable
50 W
50 W
OUT_D1+
OUT_D1-
IN_D1+
IN_D1-
EQ3
HPD_SOURCE
(0 V to 3.3 V)
DDC_EN (0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
DDET
EQ
enable
HPD level shifter
200 kW
HPD_SINK
(0 V to 5 V)
I
2
C-BUS
SLAVE
ROM
DDC BUFFER
AND
LEVEL SHIFTER
aaa-014384
SCL_SINK
SDA_SINK
Fig 2.
Functional diagram of PTN3361C
PTN3361C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1.1 — 28 July 2015
5 of 30
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