Femtoclock™ Crystal-To-LVHSTL
Frequency Synthesizer
8422002I-07
Data Sheet
General Description
The 8422002I-07 is a 2 output LVHSTL Synthesizer optimized to
generate Fibre Channel reference clock frequencies and is a
member of the family of high performance clock solutions from
IDT. Using a 26.5625MHz 18pF parallel resonant crystal, the
following frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz,
106.25MHz and 53.125MHz. The 8422002I-07 uses IDT’s 3
rd
generation low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The 8422002I-07 is packaged in a 20-pin TSSOP,
EPad package.
Features
•
•
•
•
•
•
•
•
Two LVHSTL outputs (V
OH_max
= 1.2V)
Selectable crystal oscillator interface or
LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 212.5MHz, using a 25MHz crystal
(637kHz - 10MHz): 0.59ps (typical) design target
Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Frequency Select Function Table
Inputs
Input Frequency (MHz)
26.5625
26.5625
26.5625
26.5625
23.4375
F_SEL1
0 (default)
0
1
1
0 (default)
F_SEL0
0 (default)
1
0
1
0 (default)
M Div. Value
24
24
24
24
24
N Div. Value
3
4
6
12
3
M/N Div. Value
8
6
4
2
8
Output Frequency (MHz)
212.5
159.375
106.25
53.125
187.5
Block Diagram
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
F_SEL[1:0]
0 0 ÷3 (default)
0 1 ÷4
1 0 ÷6
1 1 ÷12
2
Q0
1
nQ0
Pin Assignment
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDO
Q1
nQ1
GND
V
DD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
REF_CLK
Pulldown
26.5625MHz
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
Q1
nQ1
0
M = 24 (fixed)
422002I-07
20-Lead TSSOP, EPad
4.4mm x 6.5mm x 0.90mm
package body
G Package
Top View
MR
Pulldown
©2016 Integrated Device Technology, Inc
1
Revision A January 29, 2016
8422002I-07 Data Sheet
Table 1. Pin Descriptions
Number
1, 7
2, 20
3, 4
Name
nc
V
DDO
Q0, nQ0
Power
Output
Type
Unused
Description
No connect.
Output supply pins.
Differential output pair. LVHSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
PLL select control. When LOW, the selected reference clock is
frequency-multiplied by the PLL. When HIGH, the PLL is bypassed and the
selected reference clock is routed directly to the output dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pins.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the PLL Reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential output pair. LVHSTL interface levels.
5
MR
Input
Pulldown
6
nPLL_SEL
Input
Pulldown
8
9, 11
10, 16
12, 13
14
15
17
18, 19
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
REF_CLK
nXTAL_SEL
GND
nQ1, Q1
Power
Input
Power
Input
Input
Input
Power
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
R
PULLDOWN
Input Pulldown Resistor
©2016 Integrated Device Technology, Inc
2
Revision A January 29, 2016
8422002I-07 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
33.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Core Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
V
DD
– 0.10
1.6
Typical
3.3
3.3
1.8
Maximum
3.465
V
DD
2.0
112
10
1
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Core Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
V
DD
– 0.10
1.6
Typical
2.5
2.5
1.8
Maximum
2.625
V
DD
2.0
106
10
1
Units
V
V
V
mA
mA
mA
©2016 Integrated Device Technology, Inc
3
Revision A January 29, 2016
8422002I-07 Data Sheet
Table 3C. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
REF_CLK, MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 3D. LVHSTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
0.9
0
0.45
0.6
Typical
Maximum
1.2
0.4
0.80
1.2
Units
V
V
V
V
NOTE 1: Outputs termination with 50 to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 3E. LVHSTL DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
0.9
0
0.50
0.6
Typical
Maximum
1.2
0.4
0.90
1.2
Units
V
V
V
V
NOTE 1: Outputs termination with 50 to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
23.33
Test Conditions
Minimum
Typical
Fundamental
26.5625
28.33
50
7
MHz
Maximum
Units
pF
©2016 Integrated Device Technology, Inc
4
Revision A January 29, 2016
8422002I-07 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Parameter
Symbol
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (637kHz – 10MHz)
187.5MHz, (637kHz – 10MHz)
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (637kHz – 10MHz)
106.25MHz, (1.875MHz – 20MHz)
53.125MHz, (637kHz – 10MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N
3
N=3
275
48
40
0.59
0.53
0.56
0.56
0.66
875
52
60
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.66
170
113.33
56.66
35
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= -40°C to 85°C
Parameter
Symbol
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (637kHz – 10MHz)
187.5MHz, (637kHz – 10MHz)
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (637kHz – 10MHz)
106.25MHz, (1.875MHz – 20MHz)
53.125MHz, (637kHz – 10MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
N
3
N=3
250
48
40
0.60
0.72
0.64
0.55
0.68
650
52
60
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.66
170
113.33
56.66
35
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
©2016 Integrated Device Technology, Inc
5
Revision A January 29, 2016
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