73S8010R
Low Cost Smart Card Interface
Simplifying System Integration™
DS_8010R_022
APPLICATIONS
•
DESCRIPTION
The Teridian 73S8010R is a single smart card
interface IC that provides full electrical compliance
with ISO-7816-3 and EMV 4.0 (EMV2000)
specifications.
Interfacing with the host is done through the two-wire
2
I C bus and one interrupt output to inform the
system controller of the card presence and faults.
The card clock signal can be generated by an
on-chip oscillator using an external crystal, or by
connection to a clock signal.
The Teridian 73S8010R incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level-shifters drive the card signals with
the selected card voltage (3 V or 5 V), coming from an
internal Low Drop-Out (LDO) voltage regulator. This
LDO regulator is powered by a dedicated power
supply input, V
PC
. Digital circuitry is separately
powered by a digital power supply, V
DD
.
With its embedded LDO regulator, the Teridian
73S8010R is a cost-effective solution for any
application where a 5 V (typically -5% +10%) power
supply is available. Hardware support for auxiliary
I/O lines, C4 / C8 contacts is provided.
Emergency card deactivation is initiated upon
card extraction or upon any fault generated by
the protection circuitry. The fault can be a card
over-current, a V
DD
(digital power supply), a V
PC
(regulator power supply), a V
CC
(card power supply)
or an over-heating fault.
The card over-current circuitry is a true current detect
function, as opposed to V
CC
voltage drop detection, as
usually implemented in ICC interface ICs.
The V
DD
voltage fault has a threshold voltage that
can be adjusted with an external resistor or resistor
network. It allows automated card deactivation at a
customized V
DD
voltage threshold value. It can be
used, for instance, to match the system controller
operating voltage range.
•
•
•
•
Set-Top-Box Conditional Access and
Pay-per-View
Point of Sales & Transaction Terminals
Control Access & Identification
Multiple card and SAM reader configurations
DATA SHEET
August 2009
ADVANTAGES
•
Single smart card interface
•
IC firmware compatible with TDA8020
•
Traditional step-up converter is replaced by
an LDO regulator
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90 mA supplied to
the card)
•
Small format (5x5x0.8 mm) QFN32 package option
•
True card over-current detection
FEATURES
•
Card Interface
•
Complies with ISO-7816-3 and EMV 4.0
•
An LDO voltage regulator provides 3 V / 5 V to
the card from an external power supply input
•
ISO-7816-3 Activation / Deactivation
sequencer with emergency automated
deactivation on card removal or fault
detected by the protection circuitry
•
Protection includes 3 voltage supervisors
that detect voltage drops on V
CC
card and
on power supplies V
DD
and V
PC
•
Over-current detection 150 mA max
•
1 card detection input
•
Auxiliary I/O lines, for C4 / C8 contact
signals
Host Interface
•
Fast mode, 400 kbps I
2
C slave bus
•
8 possible devices in parallel
•
One control register and one status
register
•
Interrupt output to the host for fault
detection
•
Crystal oscillator or host clock, up to 27 MHz
6 kV ESD protection on the card interface
SO28 or QFN32 package
1
•
•
Rev. 1.6
© 2009 Teridian Semiconductor Corporation
73S8010R Data Sheet
FUNCTIONAL DIAGRAM
VDD
[20]
21
[4, 5, 6, 9,
16, 25, 32]
7, 8, 9
DS_8010R_022
VDDF_ADJ
[17]
18
GND
[2]
5
VPC
[3]
6
NC
VPC FAULT
[21]
22
[1]
4
VDD FAULT
VCC FAULT
GND
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
[18]
19
LDO
REGULATOR
&
VOLTAGE
SUPERVISORS
GND
[12]
14
GND
[15]
17
SCL
SDA
[19]
20
Int_Clk
R-C
OSC.
VCC
SAD0
SAD1
[29]
1
[30]
2
[31]
3
SAD2
[22]
23
I
2
C
DIGITAL
&
FAULT LOGIC
ICC RESET
BUFFER
[14]
16
RST
INT
ISO-7816
SEQUENCER
[23]
24
ICC CLOCK
BUFFER
[13]
15
CLK
[7]
10
PRES
XTAL
OSC
XTALIN
[24]
25
XTALOUT
CLOCK
GENERATION
OVER
TEMP
TEMP FAULT
[26]
26
[8]
11
IOUC
[27]
27
I/O
AUX1UC
[28]
28
ICC I/O BUFFERS
[11]
13
AUX1
[10]
12
AUX2UC
AUX2
Pin numbers reference the SO28 package
[Pin numbers]
reference the QFN32 Package
Figure 1: 73S8010R Block Diagram
Rev. 1.6
2
DS_8010R_022
73S8010R Data Sheet
Table of Contents
1
2
Pinout ............................................................................................................................................. 5
Electrical Specifications................................................................................................................ 8
2.1 Absolute Maximum Ratings ..................................................................................................... 8
2.2 Recommended Operating Conditions ...................................................................................... 8
2.3 Smart Card Interface Requirements ........................................................................................ 9
2.4 Digital Signals Characteristics ............................................................................................... 11
2.5 DC Characteristics ................................................................................................................ 11
2
2.6 I C Interface Characteristics .................................................................................................. 12
2.7 Voltage / Temperature Fault Detection Circuits...................................................................... 12
Applications Information ............................................................................................................. 13
3.1 Example 73S8010R Schematics ........................................................................................... 13
3.2 System Controller Interface (I
2
C Bus) .................................................................................... 14
3.3 Power Supply and Voltage Supervision ................................................................................. 17
3.4 Card Power Supply ............................................................................................................... 18
3.5 Over-temperature Monitor ..................................................................................................... 18
3.6 On-chip Oscillator and Card Clock......................................................................................... 18
3.7 Activation Sequence ............................................................................................................. 19
3.8 Deactivation Sequence ......................................................................................................... 19
3.9 Interrupt ................................................................................................................................ 20
3.10 Warm Reset .......................................................................................................................... 21
3.11 I/O Circuitry and Timing......................................................................................................... 21
Mechanical Drawings .................................................................................................................. 22
4.1 32-pin QFN ........................................................................................................................... 22
4.2 28-Pin SO ............................................................................................................................. 23
Ordering Information ................................................................................................................... 24
Related Documentation ............................................................................................................... 24
Contact Information..................................................................................................................... 24
3
4
5
6
7
Revision History .................................................................................................................................. 25
Rev. 1.6
3
73S8010R Data Sheet
DS_8010R_022
Figures
Figure 1: 73S8010R Block Diagram ......................................................................................................... 2
Figure 2: 73S8010R 32-Pin QFN Pinout .................................................................................................. 5
Figure 3: 73S8010R 28-Pin SO Pinout..................................................................................................... 5
Figure 4: Typical 73S8010R Application Schematic ............................................................................... 13
2
Figure 5: I C Bus Write Protocol ............................................................................................................ 15
2
Figure 6: I C Bus Read Protocol ............................................................................................................ 16
2
Figure 7: I C Bus Timing Diagram .......................................................................................................... 16
Figure 8: Activation Sequence ............................................................................................................... 19
Figure 9: Deactivation Sequence ........................................................................................................... 20
Figure 10: Interrupt operation due to Fault and Status Conditions .......................................................... 20
Figure 11: Warm Reset Operation ......................................................................................................... 21
Figure 12: I/O Timing Diagram ............................................................................................................... 21
Figure 13: 32-pin QFN Package Dimensions ......................................................................................... 22
Figure 14: 28-Pin SO Package Dimensions ........................................................................................... 23
Tables
Table 1: 73S8010R Pin Definitions .......................................................................................................... 6
Table 2: Absolute Maximum Device Ratings ............................................................................................ 8
Table 3: Recommended Operating Conditions ......................................................................................... 8
Table 4: DC Smart Card Interface Requirements ..................................................................................... 9
Table 5: Digital Signals Characteristics .................................................................................................. 11
Table 6: DC Characteristics ................................................................................................................... 11
2
Table 7: I C Characteristics ................................................................................................................... 12
Table 8: Voltage / Temperature Fault Detection Circuits......................................................................... 12
Table 9: Device Address Selection ........................................................................................................ 14
Table 10: Control Register Description ................................................................................................... 14
Table 11: Card Clock Rate Selection ..................................................................................................... 14
Table 12: Status Register Description .................................................................................................... 15
Table 13: I2C Bus Timing Parameters ................................................................................................... 16
Table 14: Choice of VCC Pin Capacitor ................................................................................................. 18
Table 15: Card Clock Divisor Options .................................................................................................... 18
Table 16: Order Numbers and Packaging Marks .................................................................................... 24
4
Rev. 1.6
DS_8010R_022
73S8010R Data Sheet
1 Pinout
The 73S8010R is supplied as a 32-pin QFN package and as a 28-pin SO package.
AUX2UC
AUX1UC
I/OUC
26
SAD2
SAD1
NC
SAD0
32
31
30
29
28
27
GND
GND
VPC
NC
NC
NC
PRES
I/O
1
2
3
4
5
6
7
8
25
24
23
22
NC
XTALOUT
XTALIN
INT
GND
VDD
SDA
SCL
VDDF_ADJ
TERIDIAN
73S8010R
21
20
19
18
17
10
11
12
13
14
15
VCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AUX1
AUX2
CLK
NC
Figure 2: 73S8010R 32-Pin QFN Pinout
GND
RST
SAD0
SAD1
SAD2
GND
GND
VPC
NC
NC
NC
PRES
I/O
AUX2
AUX1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
INT
GND
VDD
SDA
SCL
VDDF_ADJ
VCC
RST
CLK
73S8010R
Figure 3: 73S8010R 28-Pin SO Pinout
Rev. 1.6
NC
16
9
5
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