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Document Number: 38-07138 Rev. *N
Page 2 of 21
CY7B991
CY7B992
Pinouts
Figure 1. 32-pin PLCC pinout
TEST
V
CCQ
GND
REF
3F0
2F1
FS
3
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
4
2
1
32 31 30
29
28
27
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
CY7B991
CY7B992
26
25
24
23
22
13
21
14 15 16 17 18 19 20
FB
2Q1
3Q1
3Q0
V
CCN
V
CCN
2Q0
Pin Definitions
Signal Name
REF
FB
FS
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
V
CCN
V
CCQ
GND
I/O
I
I
I
I
I
I
I
I
O
O
O
O
PWR
PWR
PWR
Description
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. See
Table 1.
Three level function select inputs for output pair 1 (1Q0, 1Q1). See
Table 2.
Three level function select inputs for output pair 2 (2Q0, 2Q1). See
Table 2.
Three level function select inputs for output pair 3 (3Q0, 3Q1). See
Table 2.
Three level function select inputs for output pair 4 (4Q0, 4Q1). See
Table 2.
Three level select. See
Test Mode
on page 5 under the
Block Diagram Description
on page 4.
Output pair 1. See
Table 2.
Output pair 2. See
Table 2.
Output pair 3. See
Table 2.
Output pair 4. See
Table 2.
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
Document Number: 38-07138 Rev. *N
Page 3 of 21
CY7B991
CY7B992
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
Skew Select Matrix
The skew select matrix contains four independent sections. Each
section has two low skew, high fanout drivers (× Q0, × Q1), and
two corresponding three level function select (× F0, × F1) inputs.
Table 2
shows the nine possible output functions for each section
as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0t
U
selected.
Table 2. Programmable Skew Configurations
[1]
Function Selects
1F1, 2F1,
3F1, 4F1
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
1F0, 2F0,
3F0, 4F0
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
Output Functions
1Q0, 1Q1,
2Q0, 2Q1
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
3Q0, 3Q1
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Divide by 4
4Q0, 4Q1
–6t
U
–4t
U
–2t
U
0t
U
+2t
U
+4t
U
+6t
U
Inverted
VCO and Time Unit Generator
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (t
U
) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
Table 1. Frequency Range Select and t
U
Calculation
[1]
FS
[2, 3]
Divide by 2 Divide by 2
f
NOM
(MHz)
Min
15
25
40
Max
30
50
80
1
Approximate
-
t
U
=
-----------------------
f
NOM
N
Frequency (MHz) at
where N =
44
26
16
which t
U
= 1.0 ns
22.7
38.5
62.5
LOW
MID
HIGH
Notes
1. For all tristate inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to V
CC
/2.
2. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see
Logic Block Diagram).
Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see
Table 2).
The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until V
CC
has reached 4.3 V.
Document Number: 38-07138 Rev. *N
Page 4 of 21
CY7B991
CY7B992
Figure 2
shows the typical outputs with FB connected to a zero skew output.
[4]
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output
t
0
– 6t
U
t
0
– 5t
U
t
0
– 4t
U
t
0
– 3t
U
t
0
– 2t
U
t
0
– 1t
U
U
U
U
U
U
t
0
+1t
t
0
+2t
t
0
+3t
t
0
+4t
t
0
+5t
FBInput
REFInput
1Fx
2Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
3Fx
4Fx
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH
HH
– 6t
U
– 4t
U
– 3t
U
– 2t
U
– 1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
DIVIDED
INVERT
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in
Skew Select
Matrix
on page 4. For testing purposes, any of the three level
inputs can have a removable jumper to ground, or be tied LOW
through a 100
resistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (× F0 and × F1) and the waveform characteristics
of the REF input.
Note
4. FB connected to an output selected for “zero” skew (i.e., × F1 = × F0 = MID).
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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