FemtoClock® LVCMOS/Crystal-to-3.3V,
2.5V LVPECL Frequency Synthesizer
General Description
The 843004I is a 4 output LVPECL synthesizer optimized to generate
Fibre Channel reference clock frequencies. Using a 26.5625MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the two frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz. The 843004I uses IDT’s 3
rd
generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Fibre Channel jitter requirements. The 843004I
is packaged in a small 24-pin TSSOP package.
843004I
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
Four 3.3V differential LVPECL output pairs
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
Supports the following output frequencies: 212.5MHz, 187.5MHz,
159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz – 680MHz
Output skew: 50ps (maximum)
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(2.55MHz – 20MHz): 0.47ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Bank A Frequency Table
Inputs
Input Frequency (MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
F_SEL1
0
0
1
1
0
0
F_SEL0
0
1
0
1
1
0
M Div. Value
24
24
24
24
24
24
N Div. Value
3
4
6
12
4
3
M/N Div. Value
8
6
4
2
6
8
Output Frequency (MHz)
212.5
159.375
106.25
53.125
156.25
187.5
Block Diagram
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
2
Q0
1
nQ0
Q1
nQ1
Pin Assignment
nQ1
Q1
V
CCO
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
nc
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
TEST_CLK
Pulldown
26.5625MHz
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
0
Q2
nQ2
843004I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
©2014 Integrated Device Technology, Inc.
M = 24 (fixed)
Q3
nQ3
MR
Pulldown
843004I Rev B 12/9/14
1
843004I DATA SHEET
Table 1. Pin Descriptions
Number
1, 2
3, 22
4, 5
Name
nQ1, Q1
V
CCO
Q0, nQ0
Output
Power
Output
Type
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Negative supply pins.
Pulldown
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
Selects between the single-ended TEST_CLK or crystal interface as the PLL
reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
6
MR
Input
Pulldown
7
8, 18
9
10, 12
11
13,
14
15, 19
16
17
20, 21
23, 24
nPLL_SEL
nc
V
CCA
F_SEL0,
F_SEL1
V
CC
XTAL_OUT,
XTAL_IN
V
EE
TEST_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
Pulldown
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Rev B 12/9/14
2
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843004I DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
CC
-0.5V to V
CC
+ 0.5V
50mA
100mA
70C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Included in I
EE
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
130
15
Units
V
V
V
mA
mA
Table 3B. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Included in I
EE
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
120
12
Units
V
V
V
mA
mA
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
3
Rev B 12/9/14
843004I DATA SHEET
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
TEST_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
V
CC
= 3.3V
V
CC
= 2.5V
Input
High Current
Input
Low Current
V
CC
= V
IN
= 3.465V or 2.625V
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
V
IL
I
IH
I
IL
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-5
µA
Table 3D. LVPECL DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.0
0.6
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Units
µA
µA
V
NOTE 1: Outputs termination with 50
to V
CCO
– 2V.
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
Fundamental
26.5625
28.33
50
7
MHz
Maximum
Units
pF
Rev B 12/9/14
4
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
843004I DATA SHEET
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (2.55MHz – 20MHz)
159.375MHz, (1.875MHz – 20MHz)
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 3
156.25MHz, (1.875MHz – 20MHz)
106.25MHz, (637kHz – 5MHz)
53.125MHz, (637kHz – 50MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0]
00
F_SEL[1:0] = 00
300
49
42
0.47
0.52
0.52
0.62
0.67
600
51
58
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.66
170
113.33
56.66
50
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Table 5B. AC Characteristics,
V
CC
= V
CCA
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (2.55MHz – 20MHz)
159.375MHz, (1.875MHz – 20MHz)
tjit(Ø)
RMS Phase Jitter, (Random)
156.25MHz, (1.875MHz – 20MHz)
106.25MHz, (637kHz – 5MHz)
53.125MHz, (637kHz – 50MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0]
00
F_SEL[1:0] = 00
300
48
42
0.49
0.52
0.52
0.65
0.71
600
52
58
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.66
170
113.33
56.66
50
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL
FREQUENCY SYNTHESIZER
5
Rev B 12/9/14
FPGA/CPLD
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