MIC5400
Micrel
MIC5400
Dual, 8-Output, 14-Bit LED Video Display Driver
General Description
The MIC5400 consists of 2 banks of 8 LED driver outputs,
each output capable of sinking up to 30mA. Each bank is
intended to drive 8 LED pixels of the same color. Most
applications will use the MIC5400 to drive pixel clusters of 4
LEDs (RRGB.) Typically two red LEDs are used for every one
green and blue to compensate for red LED brightness.
A single external resistor sets maximum drive current. Use of
an external resistor allows different color LED banks to be
biased to the same intensity. Brightness control is digitally
programmed through the serial interface. Coarse Brightness
Control is determined by two 4-bit DACs, one for each driver
bank, limiting the full-scale output to a fraction of the maxi-
mum value. Additionally, each output has Fine Brightness
Control using 10-bit resolution PWM.
Groups of drivers can be cascaded in Daisy Chain fashion.
Open circuit output faults are detected and can be read back
from the internal Status register.
Features
• 2 banks of 8 outputs
• Output characteristics:
• Current sink: 30mA
– Programmable brightness control
• Coarse: 4-bit resolution DAC
• Fine: 10-bit resolution PWM
– Resistor sets maximum LED current to compensate
variation in LEDs
– Current limit on each output
• Full protection:
– Over-temperature shutdown
– Watchdog disables output under fault condition
– Power-on reset (all LEDs Off)
– Soft-start on power up and watchdog recovery
– Output open fault detection with status register
readback
• Output transitions are staggered to minimize supply
transients
Applications
• Outdoor video screen
• Large LED display
Ordering Information
Part Number
MIC5400BWM
MIC5400YWM
Junction Temp. Range
–40°C to +85°C
–40°C to +85°C
Package
28-Pin Wide SOIC
28-Pin Wide SOIC
Typical Application
R
SC
BCP69
MIC5400
VDDA
R
SET
Output A
SHFTCLK
SHIFTIN
SHIFTOUT
LOAD
BD_A
Logic
Control and
SRegister
Output B
V
DD
0.01µF
VDD
VDDB
BD_B
R
SC
2.2µF
330½
BCP69
330½
2.2µF
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
January 2005
1
MIC5400
MIC5400
Micrel
Pin Configuration
A4 1
A3 2
A2 3
A1 4
LOAD 5
SHFTCLK 6
VDD 7
GND 8
SHIFTIN 9
SHIFTOUT 10
B1 11
B2 12
B3 13
B4 14
28 A5
27 A6
26 A7
25 A8
24 VDDA
23 BD_A
22 GND
21 IREF
20 BD_B
19 VDDB
18 B8
17 B7
16 B6
15 B5
28-Lead SOIC
Pin Description
Pin Number
Pin
1,2,3,4
5
Pin Name
Name
A4,A3,A2,A1
LOAD
Pin Function
Function
Current Sink pins to be connected to LED cathodes
If this pin is Low, the device acts as a shift register. When this pin is High,
only the first falling edge of the clock transfers data from the Shift-Register to
the Parallel Register. The next rising edge transfers data from the Status
Register to the Shift Register
Shift-register Clock Input
Positive Supply Voltage
Ground
Shift-register Data Input
Shift-register Data Output
Current Sink pins to be connected to LED cathodes
Current Sink pins to be connected to LED cathodes
Analog Power source pins which provide current sense points for Channel A
and Channel B PNP emitter currents, independently.
Base Drive Outputs for external PNP transistors. Feedback Loop compensa-
tion requires one external capacitor at each PNP transistor collector.
Reference current output. Must be connected to an external resistor to set
the maximum current for the current sink outputs.
Base Drive Outputs for external PNP transistors. Feedback Loop compensa-
tion requires one external capacitor at each PNP transistor collector.
Analog Power source pins which provide current sense points for Channel A
and Channel B PNP emitter currents, independently.
Current Sink pins to be connected to LED cathodes
6
7
8,22
9
10
11,12,13,14
15,16,17,18
19
20
21
23
24
25,26,27,28
SHFTCLK
VDD
GND
SHIFTIN
SHIFTOUT
B1,B2,B3,B4
B5,B6,B7,B8
VDDB
BD_B
REF
BD_A
VDDA
A8,A7,A6,A5
MIC5400
2
January 2005
MIC5400
Micrel
Absolute Maximum Ratings
(Note 1)
Supply Voltage .............................................................. +7V
Input Voltage ....................................... –0.3V to V
CC
+ 0.3V
Base Drive Voltage ....................................................... +7V
Output Sink Current (per output) ................................ 35mA
Lead Temperature (soldering, 5 sec) ........................ 260°C
Junction Temperature (T
J
)(max) ............................... 125°C
Operating Ratings
(Note 2)
Supply Voltage (V
CC
) ................................ +4.75V to +5.5V
Junction Temperature (T
J
) ....................... –40°C to +125°C
Package Thermal Resistance
SOIC (θ
JC
) .......................................................... 28°C/W
SOIC (θ
JA
) ......................................................... 100°C/W
DC Electrical Characteristics
V
DD
= 4.75V to 5.5 V, T
A
= 25°C,
bold
values indicate –40°C
≤
T
A
≤
+85°C. R
BIAS
= 500Ω. Applies to all channels unless noted.
Symbol
I
OUT
∆I
OUT
I
OUT(OFF)
I
DD
I
B
V
REF
V
IH
V
IL
V
OH
V
OL
T
SHUTDOWN
Parameter
Output Sink Current
Output Current Matching
Output Off Leakage
Supply Current
PNP Base Drive Current
Reference Output Voltage
Logic 1 Input Threshold
Logic 0 Input Threshold
Logic 1 Output Level
Logic 0 Output Level
Thermal Shutdown Temperature
I
LOAD
= 1mA
I
LOAD
= 1mA
165
2.4
0.4
V
OUT
= 5V
V
DD
= 5.5V
V
BD
= 4V
I
REF
= –4mA
–1
0
7
1.9
2.2
0.8
Condition
Min
26
Typ
Max
35
7
1
2
50
2.1
Units
mA
%
µA
mA
mA
V
V
V
V
V
°C
AC Electrical Characteristics
V
DD
= 4.75V to 5.5V, T
A
= 25°C,
bold
values indicate –40°C
≤
T
A
≤
+85°C. R
BIAS
= 500Ω. Applies to all channels unless noted
Symbol
f
SHIFT
t
SET-DATA
t
HOLD-DATA
t
SET-LOAD
t
HOLD-LOAD
I
OUT(tr)
I
OUT(ttf)
t
D-SHIFT
t
r,f-OUT
t
WD-TIMEOUT
t
r,f[in]
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Parameter
Shift Frequency
Set Up Time for Data In
Hold Time for Data In
Set Up Time for Load
Hold Time for Load
Rise Time I
OUT
Fall Time I
OUT
Clock to Shift Out Delay
Shift Out Rise and Fall Time
Watch Dog Timeout Delay
Logic Input Rise and Fall Times
Conditions
Min
Typ
Max
15
Units
MHz
ns
ns
ns
ns
Note 5
Note 5
Note 5
Note 5
Note 4, 5
Note 4, 5
Rise and Fall, 50% C
LOAD
= 30pF,
Note 5
10% to 90%; C
LOAD
=30pF,
Note 5
No Shiftclock
7
13
20
13
125
50
23
10
25
200
10
ns
ns
ns
ns
µs
ns
Exceeding the absolute maximum rating may damage the device.
The device is not guaranteed to function outside its operating rating.
Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
Test circuit shown in Figure 1.
Guaranteed by design; not production tested.
January 2005
3
MIC5400
MIC5400
Micrel
Test Circuit
V
DD
= 5V
Controller
Device
Under Test
OUT
N
75Ω
V
OUT
to FET Probe (C < 1.5pF)
Figure 1. AC Output Test Circuit
Timing Diagrams
SHFTCLK
LOAD
Control Register Contents
D
N-1
D
N
Shift Register Contents
Shifting
D
N
D
N
S
N
Shifting
Status Register Contents
S
N
S
N
S
N
S
N+1
Figure 2. MIC5400 Timing Diagram
Linearity
Typical Global Full Scale Linearity
(any output)
45
40
35
I
OUT
( mA )
Linear Operating Region
(Recommended)
30
25
20
15
10
T
J
= 25°
Non-Linear
Operation
5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
I
REF
(mA)
Figure 3. Typical Global Full Scale Linearity
MIC5400
4
January 2005
MIC5400
Micrel
Functional Diagram
PWM Select (3 Bits)
PWM
Select
Select 1 of 8 in Bank A/B
PWM 1
PWM 2
PWM 3
PWM 4
PWM 5
Out 1A
Out 2A
Out 3A
Out 4A
Out 5A
Out 6A
Out 7A
Out 8A
PWM Data A (10 Bits)
PWM Data B (10 Bits)
Watchdog Enable (1 Bits)
Data and
Control Register
(36 bits)
DAC A (4 Bits)
DAC B (4 Bits)
Divisor (4 Bits)
IREF A
2X4-bit
Brightness
DAC
PWM 6
PWM 7
PWM 8
IREF B
Status A (8 Bits)
Status B (8 Bits)
PWM 1
Watchdog Status (1 Bits)
Out 1B
Out 2B
Out 3B
Out 4B
Out 5B
Out 6B
Out 7B
Out 8B
Status Register
(36 bits)
Thermal Status (1 Bits)
Mask Rev. (3 Bits)
Fixed Pattern (15 Bits)
PWM 2
PWM 3
PWM 4
PWM 5
PWM 6
PWM 7
SHIFTIN
36 Bit Shift Register
SHIFTOUT
PWM 8
SHFTCLK
LOAD
MIC5400 Functional Diagram
January 2005
5
MIC5400
PCB设计
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