Ordering number : ENA0929
LC87F5NC8A
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F5NC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrate on a single chip a number of hardware features such as 128K-byte flash ROM (onboard rewritable),
4096byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a
16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a
base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO ports (with automatic
block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex),
four 12-bit PWM channels, an 8-bit 15-channel AD converter, a system clock frequency divider, and a 29-source 10-
vector interrupt feature.
Features
Flash
ROM
•
Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
•
Block-erase in 128 byte units
• 131072 ×
8 bits
RAM
•
4096
×
9 bits
Minimum
Bus Cycle Time
•
83.3ns (12MHz)
VDD=2.8 to 5.5V
•
125ns (8MHz)
VDD=2.5 to 5.5V
•
500ns (2MHz)
VDD=2.2 to 5.5V
Note: Bus cycle time indicates the speed to read ROM.
Minimum
Instruction Cycle Time (tCYC)
•
250ns (12MHz)
VDD=2.8 to 5.5V
•
375ns (8MHz)
VDD=2.5 to 5.5V
•
1.5μs (2MHz)
VDD=2.2 to 5.5V
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 2-bit units
Ports whose I/O direction can be designated in 4-bit units
•
Normal withstand voltage input port
•
Dedicated oscillator ports
•
Reset pins
•
Power pins
64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn,
S2Pn, PWM0, PWM1, XT2)
16 (PEn, PFn)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 4, VDD1 to 4)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
92607HKIM 20070810-S00009 No. A0929-1/25
LC87F5NC8A
Timers
•
Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×2
channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed
Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
SIO
•
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
•
SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
UART:
2 channels
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2 bit in continuous transmission mode)
•
Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD
Converter: 8 bits
×
15 channels
PWM:
Multifrequency 12-bit PWM
×
4 channels
Remote
Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
No.A0929-2/25
LC87F5NC8A
Watchdog
Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Clock
Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
•
29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer0/base timer1
T0H/INT6
T1L/T1H/INT7
SIO0/UART1 receive/UART2 receive
SIO/UART1 transmit/UART2 transmit
ADC/T6/T7/PWM4, PWM5
Port 0/T4/T5/PWM2, PWM3
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine
Stack Levels: 2048 levels maximum (the stack is allocated in RAM)
High-speed
Multiplication/Division Instructions
•
16-bits
×
8-bits (5 tCYC execution time)
•
24-bits
×
16-bits (12 tCYC execution time)
•
16-bits
÷
8-bits (8 tCYC execution time)
•
24-bits
÷
16-bits (12 tCYC execution time)
Oscillation
Circuits
•
RC oscillation circuit (internal)
•
CF oscillation circuit
•
Crystal oscillation circuit
•
Multifrequency RC oscillation circuit (internal)
: For system clock
: For system clock, with internal Rf
: For low-speed system clock
: For system clock
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
No.A0929-3/25
LC87F5NC8A
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of interrupt.
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip
Debugger Function
•
Permits software debugging with the test device installed on the target board.
Package
Form
•
QIP100E (14
×
20) : “Lead-free type”
Development
Tools
•
Evaluation (EVA) chip
•
Emulator
•
On-chip-debugger
Programming
Boards
Package
QIP100E (14
×
20)
Programming boards
W87F52256Q
: LC87EV690
: EVA62S + ECB876600D + SUB875C00 + POD100QFP
ICE-B877300 + SUB875C00 + POD100QFP
: TCB87-TypeB + LC87F5NC8A
Flash
ROM Programmer
Maker
Flash Support
Group, Inc.
(Single)
Flash Support
Group, Inc.(Gang)
Model
AF9708/09/09B
(including product of Ando Electric Co.,Ltd)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
(including product of Ando Electric Co.,Ltd)
SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
Support version(Note)
Revision : After Rev.02.73
Device
LC87F76C8A
Revision : After Rev.02.29
LC87F5NC8A
Revision : After Rev.01.88
Application Version:
Our company
After 1.04
Chip Data Version:
After2.10
LC87F5NC8A
No.A0929-4/25
LC87F5NC8A
Package Dimensions
unit : mm (typ)
3151A
23.2
80
81
51
50
0.8
14.0
20.0
100
1
0.65
(0.58)
(2.7)
31
30
0.3
0.15
3.0max
0.1
SANYO : QIP100E(14X20)
17.2
No.A0929-5/25
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