CY8C20134/CY8C20234/CY8C20334
CY8C20434/CY8C20534/CY8C20634
PSoC
®
Programmable System-on-Chip™
PSoC
®
Programmable System-on-Chip™
Features
■
■
Low power CapSense
®
block
❐
Configurable capacitive sensing elements
❐
Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
Powerful Harvard-architecture processor
❐
M8C processor speeds running up to 12 MHz
❐
Low power at high speed
❐
Operating voltage: 2.4 V to 5.25 V
❐
Industrial temperature range: –40 °C to +85 °C
Flexible on-chip memory
❐
8 KB flash program storage 50,000 erase/write cycles
❐
512-Bytes SRAM data storage
❐
Partial flash updates
❐
Flexible protection modes
❐
Interrupt controller
❐
In-system serial programming (ISSP)
Complete development tools
❐
Free development tool (PSoC Designer™)
❐
Full-featured, in-circuit emulator, and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
Precision, programmable clocking
❐
Internal ±5.0% 6- / 12-MHz main oscillator
❐
Internal low speed oscillator at 32 kHz for watchdog and sleep
Programmable pin configurations
❐
Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
❐
Up to 28 analog inputs on all GPIOs
❐
Configurable inputs on all GPIOs
❐
20-mA sink current on all GPIOs
❐
Selectable, regulated digital I/O on port 1
• 3.0 V, 20 mA total port 1 source current
• 5 mA strong drive mode on port 1 versatile analog mux
❐
Common internal analog bus
❐
Simultaneous connection of I/O combinations
❐
Comparator noise immunity
❐
Low-dropout voltage regulator for the analog array
■
Additional system resources
❐
Configurable communication speeds
• I
2
C: selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: configurable between 46.9 kHz and 3 MHz
2
❐
I C slave
❐
SPI master and SPI slave
❐
Watchdog and sleep timers
❐
Internal voltage reference
❐
Integrated supervisory circuit
■
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Config LDO
PSoC
CORE
System Bus
■
Global Analog Interconnect
SRAM
512 Bytes
Interrupt
Controller
SROM
Flash 8K
Sleep and
Watchdog
CPU Core
(M8C)
■
6/12 MHz Internal Main Oscillator
■
ANALOG
SYSTEM
CapSense
Block
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-05356 Rev. *T
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 14, 2015
CY8C20134/CY8C20234/CY8C20334
CY8C20434/CY8C20534/CY8C20634
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA92181, Resources Available for CapSense
®
Controllers.
Following is an abbreviated list for CapSense devices:
■
■
Overview:
CapSense Portfolio, CapSense Roadmap.
Product Selectors:
CapSense, CapSense Plus, CapSense
Express, PSoC3 with CapSense, PSoC5 with CapSense,
PSoC4.
In addition,
PSoC Designer
offers a device selection
tool at the time of creating a new project.
Application Notes: Cypress offers CapSense application notes
covering a broad range of topics, from basic to advanced level.
Recommended application notes for getting started with
CapSense are:
❐
AN64846 – Getting Started With CapSense.
®
❐
CY8C20x34 CapSense Design Guide.
®
❐
AN2397 – CapSense Data Viewing Tools.
Technical Reference Manual (TRM):
®
❐
PSoC CY8C20x24, CY8C20x34 Family Technical
Reference Manual.
■
■
Development Kits:
❐
CY3280-20x34 Universal CapSense Controller Kit
features
a predefined control circuitry and plug-in hardware to make
prototyping and debugging easy. Programming and
I2C-to-USB Bridge hardware are included for tuning and data
acquisition.
❐
CY3280-SLM Linear Slider Module Kit
consists of five
CapSense buttons, one linear slider (with ten sensors) and
five LEDs. This module connects to any CY3280 Universal
CapSense Controller Board, including CY3280-20x34 kit.
❐
CY3280-BBM Universal CapSense Prototyping Module Kit
provides access to every signal routed to the 44-pin
connector on the attached controller board including
CY3280-20x34 kit.
Programming
❐
PSoC supports a number of different programming modes
and tools. For more information see the
General
Programming page.
■
■
PSoC Designer
PSoC Designer
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of systems based on CapSense (see
Figure 1).
With PSoC Designer, you can:
1. Drag and drop User Modules to build your hardware system
3. Configure User Module
design in the main design workspace
4. Explore the library of user modules
2. Codesign your application firmware with the PSoC hardware,
5. Review user module datasheets
using the PSoC Designer IDE C compiler
Figure 1. PSoC Designer Features
Document Number: 001-05356 Rev. *T
Page 2 of 50
CY8C20134/CY8C20234/CY8C20334
CY8C20434/CY8C20534/CY8C20634
Contents
PSoC Functional Overview .............................................. 4
PSoC Core .................................................................. 4
CapSense Analog System .......................................... 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pin Information ................................................................. 9
8-Pin SOIC Pinout ....................................................... 9
16-Pin SOIC Pinout ................................................... 10
48-Pin OCD Part Pinout ............................................ 11
16-Pin Part Pinout ..................................................... 13
24-Pin Part Pinout ..................................................... 14
32-Pin Part Pinout ..................................................... 15
28-Pin Part Pinout ..................................................... 17
30-Ball Part Pinout .................................................... 18
Electrical Specifications ................................................ 19
Absolute Maximum Ratings ....................................... 19
Operating Temperature ............................................. 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 25
Packaging Dimensions .................................................. 32
Thermal Impedances ................................................. 37
Solder Reflow Specifications ..................................... 37
Development Tool Selection ......................................... 38
Software .................................................................... 38
Development Kits ...................................................... 38
Evaluation Tools ............................................................. 38
Device Programmers ................................................. 39
Accessories (Emulation and Programming) .............. 39
Ordering Information ...................................................... 40
Ordering Code Definitions ......................................... 40
Acronyms ........................................................................ 41
Acronyms Used ......................................................... 41
Reference Documents .................................................... 41
Document Conventions ................................................. 42
Units of Measure ....................................................... 42
Numeric Conventions ................................................ 42
Glossary .......................................................................... 42
Document History Page ................................................. 47
Sales, Solutions, and Legal Information ...................... 50
Worldwide Sales and Design Support ....................... 50
Products .................................................................... 50
PSoC® Solutions ...................................................... 50
Cypress Developer Community ................................. 50
Technical Support ..................................................... 50
Document Number: 001-05356 Rev. *T
Page 3 of 50
CY8C20134/CY8C20234/CY8C20334
CY8C20434/CY8C20534/CY8C20634
PSoC Functional Overview
The PSoC family consists of many
Programmable
System-on-Chips with On-Chip Controller
devices. These
devices are designed to replace multiple traditional MCU based
system components with one low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks and programmable interconnect. This architecture
enables the user to create customized peripheral configurations
to match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The PSoC architecture for this device family, as shown in
Figure 2,
consists of three main areas: the Core, the System
Resources, and the CapSense Analog System. A common
versatile bus enables connection between I/O and the analog
system. Each CY8C20x34 PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 28 general purpose I/O (GPIO) are also
included. The GPIO provide access to the MCU and analog mux.
Figure 2. Analog System Block Diagram
ID AC
Analog Global Bus
Vr
R eferenc e
Buffer
C internal
C om parator
Mux
Mux
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, IMO, and ILO.
The CPU core, called the M8C, is a powerful processor with
speeds up to 12 MHz. The M8C is a two MIPS, 8-bit
Harvard-architecture microprocessor.
System Resources provide additional capability such as a
configurable I
2
C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The Analog System consists of the CapSense PSoC block and
an internal 1.8 V analog reference. Together they support capac-
itive sensing of up to 28 inputs.
R efs
C ap Sens e C ounters
C SC LK
IMO
C apSens e
C lock Selec t
R elaxation
O s c illator
(RO)
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins is
completed quickly and easily across multiple ports.
Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
Complex capacitive sensing interfaces such as sliders and
touch pads
Chip-wide mux that enables analog input from any I/O pin
Crosspoint connection between any I/O pin combinations
Document Number: 001-05356 Rev. *T
Page 4 of 50
CY8C20134/CY8C20234/CY8C20334
CY8C20434/CY8C20534/CY8C20634
Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. Brief statements describing the
merits of each system resource follow:
■
■
Low voltage detection (LVD) interrupts signal the application of
falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
An internal 1.8 V reference provides an absolute reference for
capacitive sensing.
The 5 V maximum input, 3 V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.
The I
2
C slave or SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires run at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■
■
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4
analog blocks.
Table 1
lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is
highlighted.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C28xxx
CY8C27x43
CY8C24x94
CY8C24x23A
CY8C23x33
CY8C22x45
CY8C21x45
CY8C21x34
CY8C21x23
CY8C20x34
CY8C20xx6
Digital
I/O
up to 64
up to 44
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
Digital
Rows
4
up to 3
2
1
1
1
2
1
1
1
0
0
Digital
Blocks
16
up to 12
8
4
4
4
8
4
4
4
0
0
Analog
Inputs
up to 12
up to 44
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
up to 8
up to 28
up to 36
Analog
Outputs
4
up to 4
4
2
2
2
0
0
0
0
0
0
Analog
Columns
4
up to 6
4
2
2
2
4
4
2
2
0
0
Analog
Blocks
12
up to
12 + 4
[1]
12
6
6
4
6
[1]
6
4
[1]
[1]
SRAM
Size
2K
1K
256
1K
256
256
1K
512
512
256
512
up to
2K
Flash
Size
32 K
16 K
16 K
16 K
4K
8K
16 K
8K
8K
4K
8K
up to
32 K
4
[1]
3
[1,2]
3
[1,2]
Notes
1. Limited analog functionality
2. Two analog blocks and one CapSense
®
.
Document Number: 001-05356 Rev. *T
Page 5 of 50
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