Operating Temperature Range ......................... -40°C to +125°C
Storage Temperature Range ........................... .-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
PARAMETER
Supply Voltage Range
Supply Current
(V
CC
= 1V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified. Typical values are at V
CC
= 5V and T
A
= +25°C.) (Note 1)
SYMBOL
V
CC
I
CC
V
TH
V
HYST
t
RD
t
RP
I
RAMP
VTH-RAMP
CONDITIONS
V
CC
≤ 5.0V
V
CC
≤ 3.3V
V
CC
≤ 2.0V
T
A
= +25°C
MIN
1.0
TYP
2.5
1.9
1.6
MAX
5.5
4.2
3.4
2.5
V
TH
+ 1.5%
V
TH
+ 2.5%
UNITS
V
µA
V
CC
Reset Threshold Accuracy
Hysteresis
V
CC
to Reset Delay
Reset Timeout Period
V
SRT
Ramp Current
V
SRT
Ramp Threshold
T
A
= -40°C to +125°C
V
CC
falling at 1mV/µs
C
SRT
= 1500pF
C
SRT
= 0
V
TH
- 1.5%
V
TH
- 2.5%
V
mV
µs
ms
nA
V
mV
4 x V
TH
80
4.375
0.275
240
0.65
33
3.00
5.75
V
SR
T = 0 to 0.65V; V
CC
= 1.6V to 5V
V
CC
= 1.6V to 5V (V
RAMP
rising)
V
RAMP
falling threshold
V
CC
≥ 1.0V, I
SINK
= 50µA
RAMP Threshold Hysteresis
RESET
Output Voltage Low
V
OL
0.3
0.3
0.4
0.8 x V
CC
0.8 x V
CC
0.8 x V
CC
1.0
0.8 x V
CC
0.8 x V
CC
0.8 x V
CC
0.8 x V
CC
0.3
0.3
0.4
V
V
µA
V
V
V
CC
≥ 2.7V, I
SINK
= 1.2mA
V
CC
≥ 4.5V, I
SINK
= 3.2mA
V
CC
≥ 1.8V, I
SOURCE
= 200µA
V
CC
≥ 4.5V, I
SOURCE
= 800µA
V
CC
> V
TH
, reset not asserted
V
CC
≥ 1.0V, I
SOURCE
= 1µA
V
CC
≥ 1.8V, I
SOURCE
= 150µA
V
CC
≥ 2.7V, I
SOURCE
= 500µA
V
CC
≥ 4.5V, I
SOURCE
= 800µA
V
CC
≥ 1.8V, I
SINK
= 500µA
V
CC
≥ 2.7V, I
SINK
= 1.2mA
V
CC
≥ 4.5V, I
SINK
= 3.2mA
RESET
Output Voltage High,
Push-Pull
RESET
Output Leakage Current,
Open-Drain
V
OH
I
LKG
V
CC
≥ 2.25V, I
SOURCE
= 500µA
RESET Output Voltage High
V
OH
RESET Output Voltage Low
V
OL
Note 1:
Devices production tested at +25°C. Overtemperature limits are guaranteed by design.
www.maximintegrated.com
Maxim Integrated │ 2
MAX6340/MAX6421–
MAX6426
Typical Operating Characteristics
Low-Power, SC70/SOT µP Reset Circuits
with Capacitor-Adjustable Reset Timeout Delay
(V
CC
= 5V, C
SRT
= 1500pF, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6421/26 toc01
MAX6421/26 toc02
RESET TIMEOUT PERIOD (ms)
SUPPLY CURRENT (µA)
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
T
A
= +25°C
T
A
= -40°C
1000
100
10
1
0.1
0.001
RESET TIMEOUT PERIOD (ms)
3.5
T
A
= +125°C
C
SRT
= 1500pF
4.25
4.20
4.15
6
0.01
0.1
1
C
SRT
(nF)
10
100
1000
4.10
-50
-25
0
25
50
75
100
125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
MAX6421/26 toc04
MAX6421/26 toc05
550
RESET TIMEOUT PERIOD (µs)
500
450
400
350
300
250
200
-50
-25
0
25
50
75
C
SRT
= 0
150
TRANSIENT DURATION (s)
125
100
75
50
25
V
TH
= 2.95V
0
200
400
600
800
RESET OCCURS
ABOVE THE CURVE
150
V
CC
TO RESET DELAY Sµs)
140
130
120
110
100
90
V
CC
FALLING AT 1mVs
100
125
0
1000
80
-50
-25
0
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
25
75
50
TEMPERATURE (°C)
100
125
POWER-UP/POWER-DOWN
CHARACTERISTIC
MAX6421/26 toc07
NORMALIZED RESET THRESHOLD
vs. TEMPERATURE
NORMALIZED RESET THRESHOLD
MAX6421/26 toc08
V
CC
V
TH
= 1.6V
1.006
1.004
1.002
1.000
0.998
0.996
0.994
1V/div
1V/div
RESET
400s/div
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
www.maximintegrated.com
Maxim Integrated │ 3
MAX6421/26 toc06
600
RESET TIMEOUT PERIOD
vs. TEMPERATURE
175
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
160
V
CC
TO RESET DELAY
vs. TEMPERATURE (V
CC
FALLING)
MAX6421/26 toc03
4.0
10,000
RESET TIMEOUT PERIOD vs. C
SRT
4.30
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX6340/MAX6421–
MAX6426
Pin Description
PIN
MAX6340
SOT23
MAX6421
MAX6422
MAX6423
SOT143
SC70
MAX6424
MAX6425
SOT23
Low-Power, SC70/SOT µP Reset Circuits
with Capacitor-Adjustable Reset Timeout Delay
MAX6426
SOT23
NAME
FUNCTION
1
3
3
5
1
SRT
Set Reset Timeout Input. Connect a capacitor between
SRT and ground to set the timeout period. Determine the
period as follows: tRP = 2.73 × 10
6
× C
SRT
+ 275µs with
t
RP
in seconds and C
SRT
in farads
Ground
Not Internally Connected. Can be connected to GND
Supply Voltage and Reset Threshold Monitor Input
RESET
changes from high to low whenever V
CC
drops
below the selected reset threshold voltage.
RESET
remains low for the reset timeout period after V
CC
exceeds
the reset threshold
RESET changes from low to high whenever V
CC
drops
below the selected reset threshold voltage. RESET
remains high for the reset timeout period after V
CC
exceeds the reset threshold
2
3
4
1
—
2
2
—
1
3
4
2
2, 3
—
5
GND
N.C.
V
CC
RESET
5
4
—
4
1
4
—
—
RESET
Detailed Description
Reset Output
The reset output is typically connected to the reset input of
a µP. A µP’s reset input starts or restarts the µP in a known
state. The MAX6340/MAX6421–MAX6426 µP superviso-
ry circuits provide the reset logic to prevent code-execu-
tion errors during power-up, power-down, and brownout
conditions (see
Typical Operating Characteristics).
RESET
changes from high to low whenever V
CC
drops
below the threshold voltage. Once V
CC
exceeds the
threshold voltage,
RESET
remains low for the capaci-
tor-adjustable reset timeout period.
The MAX6422 active-high RESET output is the inverse
logic of the active-low
RESET
output. All device outputs
are guaranteed valid for V
CC
> 1V.
The MAX6340/MAX6423/MAX6425/MAX6426 are open-
drain
RESET
outputs. Connect an external pullup resistor
to any supply from 0 to 5.5V. Select a resistor value large
enough to register a logic low when
RESET
is asserted
and small enough to register a logic high while supply-
ing all input current and leakage paths connected to the
RESET
line. A 10kΩ to 100kΩ pullup is sufficient in most
FPGA/CPLD
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