Low Skew, 1-to-5,
ICS854S015I-01
Differential-to-LVDS/LVPECL Fanout Buffer
DATA SHEET
General Description
The ICS854S015I-01 is a low skew, high performance 1-to-5, 2.5V,
3.3V Differential-to-LVPECL/LVDS Fanout Buffer. The
ICS854S015I-01 has two selectable differential clock inputs.
Guaranteed output and part-to-part skew characteristics make the
ICS854S015I-01 ideal for those applications demanding well defined
performance and repeatability.
Features
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Five differential LVPECL or LVDS output pairs
Two differential clock input pairs
CLK, nCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, HCSL
PCLK, nPCLK can accept the following input levels: LVPECL,
LVDS, CML
Either CLK or PCLK inputs can be configured to accept
single-ended inputs
Maximum output frequency: 2GHz
Additive phase jitter, RMS: 0.065ps (maximum), 3.3V,
156.25MHz, 12kHz – 5MHz)
Output Skew: 55ps (maximum)
Propagation delay: 570ps (typical) @ 3.3V
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nCLK_EN
Pulldown
Pin Assignment
D
Q
LE
0
Q0
nQ0
1
Q1
nQ1
PCLK
nPCLK
V
CC
V
CC_TAP
CLK
nCLK
1
2
3
4
5
6
7
SEL_OUT
CLK_SEL
nCLK_EN
V
EE
nQ0
Q1
Q0
PCLK
Pulldown
nPCLK
Pullup/Pulldown
CLK
Pulldown
nCLK
Pullup/Pulldown
CLK_SEL
Pulldown
24 23 22 21 20 19
18 nQ1
17
V
CC
16 V
EE
15 Q2
14 nQ2
8
nc
Q2
nQ2
V
CC_TAP
Q3
nQ3
Q4
nQ4
13 Q3
9 10 11 12
Q4
nQ4
nQ3
V
CC
ICS854S015I-01
SEL_OUT
Pulldown
24-Lead VFQFN
4mm x 4mm x 0.925
mm package body
K Package
Top View
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
1
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3, 9, 17
4
5
6
7
8
10, 11
12, 13
14, 15
16, 22
18, 19
20, 21
23
Name
PCLK
nPCLK
V
CC
V
CC_TAP
CLK
nCLK
SEL_OUT
nc
nQ4, Q4
nQ3, Q3
nQ2, Q2
V
EE
nQ1, Q1
nQ0, Q0
CLK_SEL
Input
Input
Power
Power
Input
Input
Input
Unused
Output
Output
Output
Power
Output
Output
Input
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Positive supply pins.
Power supply pin. See Table 3C.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Output select pin. When LOW, selects LVDS output levels. When HIGH, selects
LVPECL output levels. See Table 3. LVCMOS/LVTTL interface levels.
No-connect.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Negative supply pins.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, selects
PCLK, nPCLK inputs. LVTTL / LVCMOS interface levels.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Qx outputs are forced low, nQx outputs are forced high.
LVTTL / LVCMOS interface levels.
24
nCLK_EN
Input
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
VCC
/2
Parameter
Input Capacitance
Input Pulldown Resistor
Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
Ω
k
Ω
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
2
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
nCLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q[0:4]
Enabled
Enabled
Disabled; Low
Disabled; Low
Outputs
nQ[0:4]
Enabled
Enabled
Disabled; High
Disabled; High
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active
mode, the state of the outputs are a function of the PCLK, nPCLK and CLK, nCLK inputs as described in Table 3B.
Disabled
nPCLK, nCLK
PCLK, CLK
Enabled
nCLK_EN
nQ[0:4]
Q[0:4]
Figure 1. nCLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
PCLK or CLK
0
1
nPCLK or nCLK
1
0
Q[0:4]
LOW
HIGH
Outputs
nQ[0:4]
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Polarity
Non-Inverting
Non-Inverting
Table 3C. V
CC_TAP
Function Table
Outputs
Q[0:4], nQ[0:4]
LVPECL
LVPECL
LVDS
LVDS
Output Level Supply
2.5V
3.3V
2.5V
3.3V
V
CC_TAP
2.5V
3.3V
2.5V
Float
Table 3D. SEL_OUT Function Table
Input
SEL_OUT
0 (default)
1
Outputs
Q[0:4], nQ[0:4]
LVDS
LVPECL
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
3
©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
10mA
15mA
49.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
I
TAP
Parameter
Positive Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
85
5
Units
V
V
mA
mA
Table 4B. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
I
TAP
Parameter
Positive Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
78
5
Units
V
V
mA
mA
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
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©2011 Integrated Device Technology, Inc.
ICS854S015I-01 Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-LVDS/LVPECL FANOUT BUFFER
Table 4C. LVDS Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
CC
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
160
Units
V
mA
NOTE: V
CC_TAP
is left floating for 3.3V operation.
Table 4D. LVDS Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
CC
I
CC_TAP
Parameter
Positive Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
150
5
Units
V
V
mA
mA
Table 4E. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
CLK_SEL,
SEL_OUT,
nCLK_EN
CLK_SEL,
SEL_OUT,
nCLK_EN
V
CC
= 3.465V
V
CC
= 2.625V
Input High Current
V
CC
= V
IN
= 3.465V or 2.625V
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
V
IL
I
IH
I
IL
Input Low Current
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
µA
Table 4F. Differential DC Characteristics,
V
CC
= 3.3V ± 5% or V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK
Peak-to-Peak Input
Voltage
Common Mode Input
Voltage; NOTE 1
CLK, nCLK
CLK, nCLK
CLK, nCLK
CLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-10
-150
0.15
V
EE
+ 0.5
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1. Common mode voltage is defined as V
IH
.
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011
5
©2011 Integrated Device Technology, Inc.
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