SiC530
www.vishay.com
Vishay Siliconix
30 A VRPower
®
Integrated Power Stage
DESCRIPTION
The SiC530 is an integrated power stage solution optimized
for synchronous buck applications to offer high current, high
efficiency, and high power density performance. Packaged
in Vishay’s proprietary 4.5 mm x 3.5 mm MLP package,
SiC530 enables voltage regulator designs to deliver up to
30 A continuous current per phase.
The
internal
power
MOSFETs
utilize
Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC530 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and zero current detect to improve light load efficiency. The
driver is also compatible with a wide range of PWM
controllers, supports tri-state PWM, and 5 V PWM logic.
A user selectable diode emulation mode (ZCD_EN#)
function is included to improve the light load performance.
The device also supports the PS4 mode to reduce power
consumption when system operates in standby state.
FEATURES
• Thermally enhanced PowerPAK
®
MLP4535-22L
package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 30 A continuous current, 40 A at 10 ms peak
current
• High efficiency performance
• High frequency operation up to 2 MHz
• Power ON reset
• 5 V PWM logic with tri-state and hold-off
• Supports PS4 mode light load requirement for IMVP8 with
low shutdown supply current (5 V, 5 μA)
• Under voltage lockout for V
CIN
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
• INTEL IMVP-8 IA / GT core power
• Up to 18 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5V
V
DRV
V
IN
V
IN
BOOT
PHASE
V
SWH
V
CIN
ZCD_EN#
PWM
controller
Gate
driver
V
OUT
PWM
P
GND
Fig. 1 - SiC530 Typical Application Diagram
C
GND
GL
S15-2523-Rev. B, 02-Nov-15
Document Number: 62940
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC530
www.vishay.com
PINOUT CONFIGURATION
P
GND
P
GND
P
GND
V
IN
V
IN
V
IN
Vishay Siliconix
11
10
9
8
7
6
V
SWH
12
V
SWH
13
V
SWH
14
V
SWH
15
V
SWH
16
24
GL
26
P
GND
25
V
IN
5
4
3
PHASE
BOOT
N.C.
V
CIN
ZCD_EN#
23
C
GND
2
1
17
P
GND
18
P
GND
19
GL
20
P
GND
21
V
DRV
22
PWM
Fig. 2 - SiC530 Pin Configuration
PIN DESCRIPTION
PIN NUMBER
1
2
23
3
4
5
6 to 8, 25
9 to 11, 17, 18, 20, 26
12 to 16
19, 24
21
22
NAME
ZCD_EN#
V
CIN
C
GND
N.C.
BOOT
PHASE
V
IN
P
GND
V
SWH
GL
V
DRV
PWM
ZCD, PS4 control. Active low
Supply voltage for internal logic circuitry
Analog ground for the driver IC
No connection
High-side driver bootstrap voltage
Return path of high-side gate driver
Power stage input voltage. Drain of high-side MOSFET
Power ground
Switch node of the power stage
Low-side gate signal
Supply voltage for internal gate driver
PWM control input
FUNCTION
ORDERING INFORMATION
PART NUMBER
SiC530CD-T1-GE3
SiC530DB
PACKAGE
PowerPAK
®
MLP4535-22L
MARKING CODE
SiC530
Reference board
5 V PWM optimized
S15-2523-Rev. B, 02-Nov-15
Document Number: 62940
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC530
www.vishay.com
PART MARKING INFORMATION
Vishay Siliconix
=
Pin 1 Indicator
Part Number Code
Siliconix Logo
ESD Symbol
Assembly Factory Code
Year Code
Week Code
Lot Code
P/N
LL
FYWW
P/N
=
=
=
F
Y
WW
LL
=
=
=
=
Fig. 3 - SiC530 Part Marking
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
Input Voltage
Control Logic Supply Voltage
Drive Supply Voltage
Switch Node (DC voltage)
Switch Node (AC
voltage)
(1)
BOOT Voltage (DC voltage)
BOOT Voltage (AC voltage)
(2)
BOOT to PHASE (DC voltage)
BOOT to PHASE (AC voltage)
(3)
All Logic Inputs and Outputs
(PWM and ZCD_EN#)
Max. Operating Junction Temperature
Ambient Temperature
Storage Temperature
Electrostatic Discharge Protection
T
J
T
A
T
stg
Human body model, JESD22-A114
Charged device model, JESD22-C101
CONDITIONS
V
IN
V
CIN
V
DRV
V
SWH
V
BOOT
V
BOOT- PHASE
LIMIT
-0.3 to +25
-0.3 to +7
-0.3 to +7
-0.3 to +25
-8 to +32
32
40
-0.3 to +7
-0.3 to +8
-0.3 to V
CIN
+ 0.3
150
-40 to +125
-65 to +150
2000
1000
V
°C
V
UNIT
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(1)
The specification values indicated “AC” is V
SWH
to P
GND
, -8 V (< 20 ns, 10 μJ), min. and 32 V (< 50 ns), max.
(2)
The specification value indicates “AC voltage” is V
BOOT
to P
GND
, 40 V (< 50 ns) max.
(3)
The specification value indicates “AC voltage” is V
BOOT
to V
PHASE
, 8 V (< 50 ns) max.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input Voltage (V
IN
)
Drive Supply Voltage (V
DRV
)
Control Logic Supply Voltage (V
CIN
)
BOOT to PHASE (V
BOOT-PHASE
, DC voltage)
Thermal Resistance from Junction to PCB
Thermal Resistance from Junction to Case
S15-2523-Rev. B, 02-Nov-15
MINIMUM
4.5
4.5
4.5
4
-
-
TYPICAL
-
5
5
4.5
5
2.5
MAXIMUM
20
5.5
5.5
5.5
-
-
°C/W
V
UNIT
Document Number: 62940
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC530
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER
POWER SUPPLY
Control Logic Supply Current
I
VCIN
V
PWM
= FLOAT
V
PWM
= FLOAT, V
ZCD_EN#
= 0 V
f
S
= 300 kHz, D = 0.1
f
S
= 300 kHz, D = 0.1
f
S
= 1 MHz, D = 0.1
V
PWM
= V
ZCD
_
EN#
= FLOAT,
T
A
= -10 °C to +100 °C
I
F
= 2 mA
-
-
-
-
-
-
80
120
300
7
20
5
-
-
-
15
-
9
μA
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
UNIT
Drive Supply Current
PS4 Mode Supply Current
BOOTSTRAP SUPPLY
Bootstrap Diode Forward Voltage
PWM CONTROL INPUT
Rising Threshold
Falling Threshold
Tri-state Voltage
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold
Hysteresis
Tri-state Falling Threshold
Hysteresis
PWM Input Current
ZCD_EN# CONTROL INPUT
Rising Threshold
Falling Threshold
Tri-state Voltage
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold
Hysteresis
Tri-state Falling Threshold
Hysteresis
ZCD_EN# Input Current
PS4 Exit Latency
TIMING SPECIFICATIONS
Tri-State to GH/GL Rising
Propagation Delay
Tri-state Hold-Off Time
GH - Turn Off Propagation Delay
GH - Turn On Propagation Delay
(Dead time rising)
GL - Turn Off Propagation Delay
GL - Turn On Propagation Delay
(Dead time falling)
PWM Minimum On-Time
PROTECTION
Under Voltage Lockout
Under Voltage Lockout Hysteresis
I
VDRV
I
VCIN
+ I
VDRV
V
F
V
TH_PWM_R
V
TH_PWM_F
V
TRI
V
TRI_TH_R
V
TRI_TH_F
V
HYS_TRI_R
V
HYS_TRI_F
I
PWM
mA
μA
-
3.6
0.72
-
1.1
3.4
-
-
-
3.9
1
2.5
1.35
3.7
325
250
-
-
3.6
1.4
2.5
1.8
3.15
375
450
-
-
-
0.65
4.2
1.3
-
1.6
4
-
V
V
PWM
= FLOAT
V
mV
-
350
-350
3.9
1.7
-
2.1
3.4
-
mV
V
HYS_TRI_ZCD#_F
I
ZCD_EN#
t
PS4EXIT
t
PD_TRI_R
t
TSHO
t
PD_OFF_GH
t
PD_ON_GH
t
PD_OFF_GL
t
PD_ON_GL
t
PWM_ON_MIN.
V
CIN
rising, on threshold
V
CIN
falling, off threshold
No load, see fig. 5
V
ZCD_EN#
= 5 V
V
ZCD_EN#
= 0 V
-
-
-
-
-
100
-100
5
μA
μs
μA
V
PWM
= 5 V
V
PWM
= 0 V
-
-
3.3
1.1
-
1.5
2.9
-
V
TH_ZCD_EN#_R
V
TH_ZCD_EN#_F
V
TRI_ZCD_EN#
V
TRI_ZCD_EN#_R
V
TRI_ZCD_EN#_F
V
HYS_TRI_ZCD#_R
V
ZCD_EN#
= FLOAT
V
-
-
-
-
-
-
30
-
2.4
-
20
150
20
20
20
20
-
3.4
2.9
500
-
-
-
-
-
-
-
3.9
-
-
ns
V
UVLO
V
UVLO_HYST
V
mV
Notes
(1)
Typical limits are established by characterization and are not production tested.
(2)
Guaranteed by design.
S15-2523-Rev. B, 02-Nov-15
Document Number: 62940
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC530
www.vishay.com
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V
PWM_TH_R
the low-side is turned OFF and the high-side is
turned ON. When PWM input is driven below V
PWM_TH_F
the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC530 to
pull the PWM input into the tri-state region (see definition of
PWM logic and tri-state, fig. 5). If the PWM input stays in this
region for the tri-state hold-off period, t
TSHO
, both high-side
and low-side MOSFETs are turned OFF. The function allows
the VR phase to be disabled without negative output voltage
swing caused by inductor ringing and saves a Schottky
diode clamp. The PWM and tri-state regions are separated
by hysteresis to prevent false triggering. The SiC530
incorporates PWM voltage thresholds that are compatible
with 5 V logic.
Diode Emulation Mode and PS4 Mode (ZCD_EN#)
The ZCD_EN# pin enables or disables diode emulation
mode. When ZCD_EN# is driven below V
TH_ZCD_EN#_F
, diode
emulation is allowed. When ZCD_EN# is driven above
V
TH_ZCD_EN#_R
, continuous conduction mode is forced.
Diode emulation mode allows for higher converter efficiency
under light load situations. With diode emulation active, the
SiC530 will detect the zero current crossing of the output
inductor and turn off the low-side MOSFET. This ensures
that discontinuous conduction mode (DCM) is achieved.
Diode emulation is asynchronous to the PWM signal,
therefore, the SiC530 will respond to the ZCD_EN# input
immediately after it changes state.
The ZCD_EN# pin can be floated resulting in a high
impedance state. High impedance on the input of ZCD_EN#
combined with a tri-stated PWM output will shut down the
SiC530, reducing current consumption to typically 5 μA.
This is an important feature in achieving the low standby
current requirements required in the PS4 state in ultrabooks
and notebooks.
Voltage Input (V
IN
)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (V
SWH
and PHASE)
The switch node, V
SWH
, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, V
SWH
. This pin
is to be used exclusively as the return pin for the BOOT
capacitor.
Ground Connections (C
GND
and P
GND
)
P
GND
(power ground) should be externally connected to
C
GND
(control signal ground). The layout of the printed circuit
board should be such that the inductance separating C
GND
and P
GND
is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V.
Control and Drive Supply Voltage Input (V
DRV
, V
CIN
)
V
CIN
is the bias supply for the gate drive control IC. V
DRV
is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC530 has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning ON from tuning ON until the other
MOSFET’s gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
OFF, before the other can be turned ON. This feature helps
to adjust dead time as gate transitions change with respect
to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC530 also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device.
Vishay Siliconix
S15-2523-Rev. B, 02-Nov-15
Document Number: 62940
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
