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DS181 (v1.1) November 7, 2011
Advance Product Specification
www.xilinx.com
1
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 2:
Recommended Operating Conditions
(1)
Symbol
V
CCINT
V
CCAUX
V
CCO(2)(4)
V
CCBRAM
V
CCBATT(3)
V
IN
I
IN(5)
Notes:
1.
2.
3.
4.
5.
All voltages are relative to ground.
Configuration data is retained even if V
CCO
drops to 0V.
V
CCBATT
is required only when using bitstream encryption. If battery is not used, connect V
CCBATT
to either ground or V
CCAUX
.
Includes V
CCO
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
A total of 100 mA per bank should not be exceeded.
Description
Internal supply voltage relative to GND, T
j
= 0°C to +85°C
For -2L (0.9V) devices: internal supply voltage relative to GND, T
j
= 0°C to +85°C
Auxiliary supply voltage relative to GND, T
j
= 0°C to +85°C
Supply voltage for 3.3V HR I/O banks relative to GND, T
j
= 0°C to +85°C
Block RAM supply voltage
Battery voltage relative to GND, T
j
= 0°C to +85°C
I/O input voltage relative to GND, T
j
= 0°C to +85°C
Maximum current through any pin in a powered or unpowered bank when forward
biasing the clamp diode.
Min
0.95
0.87
1.71
1.14
0.95
1.0
GND – 0.20
–
Max
1.05
0.93
1.89
3.47
1.05
1.89
V
CCO
+ 0.2
10
Units
V
V
V
V
V
V
V
mA
Table 3:
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRI
I
REF
I
L
C
IN(2)
Description
Data retention V
CCINT
voltage (below which configuration data might be lost)
Data retention V
CCAUX
voltage (below which configuration data might be lost)
V
REF
leakage current per pin
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 3.3V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 2.5V
Min
Typ
(1)
Max
Units
V
V
µA
µA
pF
µA
µA
µA
µA
µA
µA
µA
nA
I
RPU
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.8V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.5V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.2V
Pad pull-down (when selected) @ V
IN
= 3.3V
Pad pull-down (when selected) @ V
IN
= 1.8V
Battery supply current
Temperature diode ideality factor
Series resistance
1.0002
2
I
RPD
I
BATT(3)
n
r
Notes:
1.
2.
3.
–
Typical values are specified at nominal voltage, 25°C.
This measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C.
DS181 (v1.1) November 7, 2011
Advance Product Specification
www.xilinx.com
2
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Important Note
Typical values for quiescent supply current are specified at nominal voltage, 85°C junction temperatures (T
j
). Xilinx
recommends analyzing static power consumption at T
j
= 85°C because the majority of designs operate near the high end of
the commercial temperature range. Quiescent supply current is specified by speed grade for Artix-7 devices. Use the
XPOWER™ Estimator (XPE) spreadsheet tool (download at
http://www.xilinx.com/power)
to calculate static power
consumption for conditions other than those specified in
Table 4.
Table 4:
Typical Quiescent Supply Current
Speed Grade
Symbol
Description
Device
-3
I
CCINTQ
Quiescent V
CCINT
supply current
XC7A8
XC7A15
XC7A30T
XC7A50T
XC7A100T
XC7A200T
XC7A350T
I
CCOQ
Quiescent V
CCO
supply current
XC7A8
XC7A15
XC7A30T
XC7A50T
XC7A100T
XC7A200T
XC7A350T
I
CCAUXQ
Quiescent V
CCAUX
supply current
XC7A8
XC7A15
XC7A30T
XC7A50T
XC7A100T
XC7A200T
XC7A350T
I
CCBRAMQ
Quiescent V
CCBRAM
supply current
XC7A8
XC7A15
XC7A30T
XC7A50T
XC7A100T
XC7A200T
XC7A350T
1.0V
-2/-2L
-1
0.9V
-2L
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (T
j
).
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or
XPOWER Analyzer (XPA) tools.
DS181 (v1.1) November 7, 2011
Advance Product Specification
www.xilinx.com
3
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is V
CCINT
, V
CCBRAM
, V
CCAUX
, and V
CCO
to achieve minimum current draw and
ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If V
CCINT
and V
CCBRAM
have the same recommended voltage levels then both can be powered by the same
supply and ramped simultaneously. If V
CCAUX
and V
CCO
have the same recommended voltage levels then both can be
powered by the same supply and ramped simultaneously.
For V
CCO
voltages of 3.3V in HR I/O banks and configuration bank 0:
•
•
The voltage difference between V
CCO
and V
CCAUX
must not exceed 2.625V for longer than T
VCCO2VCCAUX
for each
power-on/off cycle to maintain device reliability levels.
The T
VCCO2VCCAUX
time can be allocated in any percentage between the power-on and power-off ramps.
There are no sequencing requirements for the GTP transceiver supplies with respect to the other FPGA supply voltages.
Table 5
shows the minimum current, in addition to I
CCQ
, that are required by Artix-7 devices for proper power-on and
configuration. If the current minimums shown in
Table 4
and
Table 5
are met, the device powers on after all three supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V
CCINT
is
applied.
Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies.
Table 5:
Power-On Current for Artix-7 Devices
Device
XC7A8
XC7A15
XC7A30T
XC7A50T
XC7A100T
XC7A200T
XC7A350T
Notes:
1.
2.
Typical values are specified at nominal voltage, 25°C.
Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at
http://www.xilinx.com/power)
to calculate maximum power-on currents.
I
CCINTMIN
Typ
(1)
I
CCAUXMIN
Typ
(1)
I
CCOMIN
Typ
(1)
I
CCBRAM
Typ
(1)
Units
mA
mA
mA
mA
mA
mA
mA
Table 6:
Power Supply Ramp Time
Symbol
T
VCCINT
T
VCCO
T
VCCAUX
T
VCCBRAM
T
VCCO2VCCAUX
Notes:
1.
Based on 240,000 power cycles with nominal V
CCO
of 3.3V or 36,500 power cycles with worst case V
CCO
of 3.465V.
Description
Ramp time from GND to 90% of V
CCINT
Ramp time from GND to 90% of V
CCO
Ramp time from GND to 90% of V
CCAUX
Ramp time from GND to 90% of V
CCBRAM
Allowed time per power cycle for V
CCO
– V
CCAUX
2.625V
Conditions
Min
0.2
0.2
0.2
0.2
Max
50
50
50
50
500
800
Units
ms
ms
ms
ms
ms
T
J
= 100°C
(1)
T
J
= 85°C
(1)
–
–
DS181 (v1.1) November 7, 2011
Advance Product Specification
www.xilinx.com
4
Artix-7 FPGAs Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the recommended
operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum V
CCO
with the respective V
OL
and
V
OH
voltage levels shown. Other standards are sample tested.
Table 7:
SelectIO DC Input and Output Levels
(1)
I/O Standard
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
HSTL I
(5)
HSTL II
(5)
DIFF HSTL I
(5)
DIFF HSTL II
(5)
SSTL135
DIFF SSTL135
SSTL18 I
SSTL18 II
DIFF SSTL18 I
DIFF SSTL18 II
SSTL15
Notes:
1.
2.
3.
4.
5.
6.
Tested according to relevant specifications.
Supported drive strengths of 4, 8, 12, 16, or 24 mA.
Supported drive strengths of 4, 8, 12, or 16 mA.
Supported drive strengths of 4, 8, or 12 mA.
Applies to both 1.5V and 1.8V HSTL.
For detailed interface specific DC voltage levels, see