74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Rev. 4 — 7 November 2011
Product data sheet
1. General description
The 74ABT823 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE) and master
reset input (MR) which are ideal for parity bus interfacing in systems using many
microprocessors.
The 74ABT823 is designed to eliminate the extra packages required to buffer existing
registers and provide extra data width for wider data and address paths of buses carrying
parity.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output Q of the flip-flop.
2. Features and benefits
High-speed parallel registers with positive edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and
32
mA
Power-on 3-state
Power-on reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT823D
74ABT823DB
74ABT823PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads;
body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT340-1
SOT355-1
Type number
NXP Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
4. Functional diagram
1
11
2
3
4
5
6
7
8
9
10
MR
D0
D1
D2
D3
D4
D5
D6
D7
D8
CP
13
1
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CE
14
001aaa847
EN
R
G1
1C2
23
22
21
20
19
18
17
16
15
001aaa848
11
14
23
22
21
20
19
18
17
16
15
7
8
9
10
3
4
5
6
2
13
2D
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74ABT823
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
2 of 17
NXP Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
D0
D1
D2
D3
D4
MR
R
R
R
R
R
CE
D
Q
D
Q
D
Q
D
Q
D
Q
CP
FF0
CP
FF1
CP
FF2
CP
FF3
CP
FF4
CP
OE
Q0
D5
D6
Q1
D7
Q2
D8
Q3
Q4
D
R
Q
D
R
Q
D
R
Q
D
R
Q
CP
FF5
CP
FF6
CP
FF7
CP
FF8
Q5
Q6
Q7
Q8
001aac444
Fig 3.
Logic diagram
74ABT823
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
3 of 17
NXP Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
5. Pinning information
5.1 Pinning
74ABT823
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
15 Q8
14 CE
13 CP
001aal300
D8 10
MR 11
GND 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
OE
D0, D1, D2, D3, D4, D5, D6, D7, D8
MR
GND
CP
CE
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9, 10
11
12
13
14
24
Description
output enable input (active LOW)
data input
master reset input (active LOW)
ground (0 V)
clock pulse input (active rising edge)
clock enable input (active LOW)
data output
positive supply voltage
Q8, Q7, Q6, Q5, Q4, Q3, Q3, Q2, Q1, Q0 15, 16, 17, 18, 19, 20, 21, 22, 23
74ABT823
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
4 of 17
NXP Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
6. Functional description
6.1 Function table
Table 3.
Input
OE
L
L
L
L
H
[1]
Function table
[1]
Output
MR
L
H
H
H
X
CE
X
L
L
H
X
CP
X
NC
X
Dn
X
h
l
X
X
Qn
L
H
L
NC
Z
hold
high-impedance
clear
load and read data
Operating mode
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
= LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
74ABT823
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 7 November 2011
5 of 17
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