512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512
Data Sheet
SST serial flash family features a four-wire, SPI-compatible interface that allows
for a low pin-count package occupying less board space and ultimately lowering
total system costs. SST25VF512 SPI serial flash memory is manufactured with
SST's proprietary, high-performance CMOS SuperFlash technology. The split-
gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
Features
• Single 2.7-3.6V Read and Write Operations
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• End-of-Write Detection
– Software Status
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• 20 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
• Packages Available
– 8-lead SOIC (4.9mm x 6mm)
– 8-contact WSON
• Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
• All non-Pb (lead-free) devices are RoHS compliant
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25076A
10/11
512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512
Data Sheet
Product Description
SST’s serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count
package occupying less board space and ultimately lowering total system costs. SST25VF512 SPI
serial flash memory is manufactured with SST’s proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
The SST25VF512 device significantly improves performance, while lowering power consumption. The
total energy consumed is a function of the applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or Program operation is less than alternative
flash memory technologies. The SST25VF512 device operates with a single 2.7-3.6V power supply.
The SST25VF512 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1
for the pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25076A
10/11
2
512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512
Data Sheet
Block Diagram
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
1192 B1.5
CE#
SCK
SI
SO
WP#
HOLD#
©2011 Silicon Storage Technology, Inc.
DS25076A
10/11
3
512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512
Data Sheet
Pin Description
CE#
SO
WP#
VSS
1
2
8
7
VDD
HOLD#
SCK
SI
CE#
SO
WP#
VSS
1
8
VDD
HOLD#
SCK
SI
2
7
Top View
3
4
6
5
1192 08-soic P1.4
Top View
3
6
4
5
1192 08-wson P1a.6
8-lead SOIC
8-contact WSON
Figure 1:
Pin Assignments
Table 1:
Pin Description
Symbol Pin Name
SCK
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
To temporarily stop serial communication with SPI flash memory without resetting the
device.
To provide power supply (2.7-3.6V).
SI
SO
CE#
WP#
HOLD#
V
DD
V
SS
Serial Data
Input
Serial Data
Output
Chip Enable
Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
Hold
Power Sup-
ply
Ground
T1.7 25076
©2011 Silicon Storage Technology, Inc.
DS25076A
10/11
4
512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512
Data Sheet
Memory Organization
The SST25VF512 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay
blocks.
Device Operation
The SST25VF512 is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF512 supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
CE#
MODE 3
MODE 3
MODE 0
SCK
SI
SO
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DON T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
1192 F34.6
HIGH IMPEDANCE
Figure 2:
SPI Protocol
©2011 Silicon Storage Technology, Inc.
DS25076A
10/11
5
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