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COM20019I-HD: 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小383KB，共66页; 制造商Microchip(微芯科技); 官网地址https://www.microchip.com; 标准

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COM20019I-HD在线购买

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	COM20019I-HD	-	-	点击查看	点击购买

COM20019I-HD规格参数

参数名称	属性值
是否Rohs认证	符合
包装说明	LFQFP, QFP48,.28SQ
Reach Compliance Code	compliant
地址总线宽度	3
边界扫描	NO
总线兼容性	ISA; RS485
最大时钟频率	20 MHz
通信协议	SYNC, BYTE
最大数据传输速率	0.0390625 MBps
外部数据总线宽度	8
JESD-30 代码	S-PQFP-G48
长度	7 mm
低功率模式	YES
DMA 通道数量
I/O 线路数量
串行 I/O 数
端子数量	48
片上数据RAM宽度	8
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装等效代码	QFP48,.28SQ
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
RAM（字数）	1024
筛选级别	TS 16949
座面最大高度	1.6 mm
最大供电电压	5.5 V
最小供电电压	4.5 V
标称供电电压	5 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
宽度	7 mm
uPs/uCs/外围集成电路类型	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches	1

文档解析

这份文档是关于SMSC COM20019I芯片的数据手册，它是一种成本效益高的ARCNET (ANSI 878.1) 控制器，具有2K x 8的片上RAM。以下是一些值得关注的技术信息：

产品特性：
- 支持最高312.5 Kbps的数据速率。
- 可编程的重配置时间。
- 28引脚PLCC和48引脚TQFP封装，也有符合RoHS标准的无铅封装。
- 适用于工业/工厂/楼宇自动化和交通应用。
- 确定性ARCNET协议，符合ANSI 878.1标准。
- 与所有微控制器或微处理器灵活的接口。
- 自动检测微控制器接口类型。
- 2Kx8片上双端口RAM。
- 命令链式传输，用于数据包排队。
- 内部时钟缩放，用于调整网络速度。
- 工作温度范围-40°C至+85°C。
订购信息：
- 提供了不同封装类型的部件编号。
电路图和时序：
- 包括了多种微控制器接口电路图和RS-485接口的示例。
- 提供了详细的时序图表，用于指导设计和确保兼容性。
内部寄存器和RAM：
- 描述了内部寄存器的功能和配置，以及如何通过地址指针访问内部RAM。
协议描述：
- 详细描述了基于令牌传递的网络协议，包括数据速率、网络重配置、广播消息和超时功能。
系统描述：
- 介绍了微控制器接口和传输媒体接口，包括背板配置和差分驱动器配置。
功能描述：
- 包括微序列器、状态/命令寄存器、重配置定时器、节点ID逻辑等的详细功能描述。
操作描述：
- 提供了电气特性和最大保证等级的详细信息。
封装轮廓：
- 提供了28引脚PLCC和48引脚TQFP封装的详细尺寸和参数。
附录：
- 包含了对NOSYNC和EF位功能的解释，这些功能影响初始化过程中的同步命令和内部操作时序。
应用示例：
- 提供了一个接口电路图示例，展示了如何将COM20019I连接到ISA总线。
授权分销商信息：
- 文档末尾提供了Mouser Electronics作为授权分销商的链接，用于查看定价、库存、交付和生命周期信息。

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COM20019I

Cost Competitive

ARCNET (ANSI 878.1)

Controller with 2K x 8

On-Chip RAM

Datasheet

Product Features

New Features:

−

Data Rates up to 312.5 Kbps

−

Programmable Reconfiguration Times

Eight, 256 Byte Pages Allow Four Pages TX and

RX Plus Scratch-Pad Memory

Next ID Readable

Internal Clock Scaler for Adjusting Network

Speed

Operating Temperature Range of -40

C to +85

Self-Reconfiguration Protocol

Supports up to 255 Nodes

Supports Various Network Topologies (Star,

Tree, Bus...)

CMOS, Single +5V Supply

Duplicate Node ID Detection

Powerful Diagnostics

Receive All Packets Mode

Flexible Media Interface:

−

RS485 Differential Driver Interface For Low Cost,

Low Power, High Reliability

28 Pin PLCC and 48 Pin TQFP Packages; Lead-

free RoHS Compliant Packages also Available

Ideal for Industrial/Factory/Building Automation

and Transportation Applications

Deterministic, (ANSI 878.1), Token Passing

ARCNET Protocol

Minimal Microcontroller and Media Interface

Logic Required

Flexible Interface For Use With All

Microcontrollers or Microprocessors

Automatically Detects Type of Microcontroller

Interface

2Kx8 On-Chip Dual Port RAM

Command Chaining for Packet Queuing

Sequential Access to Internal RAM

Software Programmable Node ID

ORDERING INFORMATION

Order Numbers:

COM20019ILJP for 28 pin PLCC package; COM20019I-DZD for 28 pin PLCC lead-free RoHS Compliant package

COM20019I-HD for 48 pin TQFP package; COM20019I-HT for 48 pin TQFP lead-free RoHS Compliant package

SMSC COM20019I

Page 1

Rev. 09-25-07

DATASHEET

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

Rev. 09-25-07

Page 2

SMSC COM20019I

DATASHEET

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

TABLE OF CONTENTS

Chapter 1

Chapter 2

Chapter 3

Chapter 4

GENERAL DESCRIPTION..................................................................................................... 5

PIN CONFIGURATIONS........................................................................................................ 6

DESCRIPTION OF PIN FUNCTIONS.................................................................................... 8

PROTOCOL DESCRIPTION ............................................................................................... 11

4.1

NETWORK PROTOCOL............................................................................................................................11

4.2

DATA RATES.............................................................................................................................................11

4.3

NETWORK RECONFIGURATION .............................................................................................................11

4.4

BROADCAST MESSAGES........................................................................................................................12

4.5

EXTENDED TIMEOUT FUNCTION ...........................................................................................................12

4.5.1

Response Time ...................................................................................................................................12

4.5.2

Idle Time .............................................................................................................................................12

4.5.3

Reconfiguration Time ..........................................................................................................................13

4.6

LINE PROTOCOL ......................................................................................................................................13

4.6.1

Invitations To Transmit........................................................................................................................13

4.6.2

Free Buffer Enquiries ..........................................................................................................................13

4.6.3

Data Packets.......................................................................................................................................13

4.6.4

Acknowledgements .............................................................................................................................14

4.6.5

Negative Acknowledgements ..............................................................................................................14

Chapter 5

SYSTEM DESCRIPTION ..................................................................................................... 15

5.1

MICROCONTROLLER INTERFACE..........................................................................................................15

5.1.1

High Speed CPU Bus Timing Support ................................................................................................18

5.2

TRANSMISSION MEDIA INTERFACE ......................................................................................................19

5.2.1

Backplane Configuration .....................................................................................................................19

5.2.2

Differential Driver Configuration ..........................................................................................................20

5.2.3

Programmable TXEN Polarity .............................................................................................................20

Chapter 6

FUNCTIONAL DESCRIPTION............................................................................................. 23

6.1

MICROSEQUENCER.................................................................................................................................23

6.2

INTERNAL REGISTERS............................................................................................................................24

6.2.1

Interrupt Mask Register (IMR) .............................................................................................................24

6.2.2

Data Register ......................................................................................................................................24

6.2.3

Tentative ID Register ..........................................................................................................................25

6.2.4

Node ID Register.................................................................................................................................25

6.2.5

Next ID Register..................................................................................................................................25

6.2.6

Status Register....................................................................................................................................25

6.2.7

Diagnostic Status Register ..................................................................................................................26

6.2.8

Command Register .............................................................................................................................26

6.2.9

Address Pointer Registers ..................................................................................................................26

6.2.10

Configuration Register.....................................................................................................................26

6.2.11

Sub-Address Register .....................................................................................................................26

6.2.12

Setup 1 Register..............................................................................................................................26

6.2.13

Setup 2 Register..............................................................................................................................27

6.3

INTERNAL RAM ........................................................................................................................................35

6.3.1

Sequential Access Memory.................................................................................................................35

6.3.2

Access Speed .....................................................................................................................................35

6.4

SOFTWARE INTERFACE..........................................................................................................................35

6.4.1

Selecting RAM Page Size ...................................................................................................................36

6.4.2

Transmit Sequence .............................................................................................................................37

6.4.3

Receive Sequence ..............................................................................................................................38

6.5

COMMAND CHAINING..............................................................................................................................39

6.5.1

Transmit Command Chaining .............................................................................................................40

6.5.2

Receive Command Chaining ..............................................................................................................40

6.6

RESET DETAILS .......................................................................................................................................41

6.6.1

Internal Reset Logic ............................................................................................................................41

6.7

INITIALIZATION SEQUENCE ....................................................................................................................41

6.7.1

Bus Determination...............................................................................................................................41

6.8

IMPROVED DIAGNOSTICS ......................................................................................................................42

6.8.1

Normal Results:...................................................................................................................................43

SMSC COM20019I

Page 3

Rev. 09-25-07

DATASHEET

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

6.8.2

Abnormal Results:...............................................................................................................................43

6.9

OSCILLATOR ............................................................................................................................................43

Chapter 7

7.1

7.2

OPERATIONAL DESCRIPTION .......................................................................................... 45

MAXIMUM GUARANTEED RATINGS*......................................................................................................45

DC ELECTRICAL CHARACTERISTICS ....................................................................................................45

Chapter 8

Chapter 9

9.1

9.2

10.1

10.2

TIMING DIAGRAMS............................................................................................................. 48

Package Outlines ................................................................................................................. 60

28 Pin PLCC Package Outline and Parameters.........................................................................................60

48 Pin TQFP Package Outline and Parameters.........................................................................................61

Chapter 10

Chapter 11

APPENDIX A........................................................................................................................ 62

NOSYNC Bit ...........................................................................................................................................62

EF Bit......................................................................................................................................................62

APPENDIX B:....................................................................................................................... 65

LIST OF FIGURES

Figure 3.1 - COM20019I OPERATION ........................................................................................................................10

Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ............................................16

Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE...................................17

Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................18

Figure 5.4 - COM20019I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS...........................................20

Figure 5.5 - INTERNAL BLOCK DIAGRAM ..................................................................................................................21

Figure 6.1 - SEQUENTIAL ACCESS OPERATION ......................................................................................................35

Figure 6.2 - RAM BUFFER PACKET CONFIGURATION .............................................................................................37

Figure 6.3 - COMMAND CHAINING STATUS REGISTER QUEUE..............................................................................39

Figure 7.1 - AC MEASUREMENTS ..............................................................................................................................47

Figure 8.1 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................48

Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................49

Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................50

Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................51

Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................52

Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................53

Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................54

Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................55

Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ......................................56

Figure 8.10 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................57

Figure 8.11 - BACKPLANE MODE TRANSMIT OR RECEIVE TIMING.......................................................................58

Figure 8.12 - TTL INPUT TIMING ON XTAL1 PIN .......................................................................................................59

Figure 8.13 - RESET AND INTERRUPT TIMING ........................................................................................................59

Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT ........................................................................................63

Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS .............................................................65

LIST OF TABLES

Table 5.1 - Typical Media .............................................................................................................................................22

Table 6.1 - Read Register Summary.............................................................................................................................23

Table 6.2 - Write Register Summary ............................................................................................................................24

Table 6.3 - Status Register ...........................................................................................................................................27

Table 6.4 - Diagnostic Status Register..........................................................................................................................28

Table 6.5 - Command Register.....................................................................................................................................29

Table 6.6 - Address Pointer High Register ....................................................................................................................30

Table 6.7 - Address Pointer Low Register.....................................................................................................................30

Table 6.8 - Sub Address Register .................................................................................................................................31

Table 6.9 - Configuration Register ................................................................................................................................31

Table 6.10 - Setup 1 Register .......................................................................................................................................32

Table 6.11 - Setup 2 Register .......................................................................................................................................33

Rev. 09-25-07

Page 4

SMSC COM20019I

DATASHEET

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Chapter 1

GENERAL DESCRIPTION

SMSC's COM20019I is a member of the family of Embedded ARCNET Controllers from Standard

Microsystems Corporation. The device is a general purpose communications controller for networking

microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments

using an ARCNET protocol engine. The flexible microcontroller and media interfaces, eight- page message

support, and extended temperature range of the COM20019I make it the only true network controller

optimized for use in industrial, embedded, and automotive applications. Using an ARCNET protocol

engine is the ideal solution for embedded control applications because it provides a deterministic token-

passing protocol, a highly reliable and proven networking scheme, and a data rate of up to 312.5 Kbps

when using the COM20019I.

A token-passing protocol provides predictable response times because each network event occurs within a

predetermined time interval, based upon the number of nodes on the network. The deterministic nature of

ARCNET is essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the

Command Chaining feature, the maximum data rate, and the internal diagnostics make the COM20019I

the highest performance embedded communications device available. With only one COM20019I and one

microcontroller, a complete communications node may be implemented.

For more details on the ARCNET protocol engine and traditional dipulse signaling schemes,

please refer to the ARCNET Local Area Network Standard, available from Standard Microsystems

Corporation or the ARCNET Designer's Handbook, available from Datapoint Corporation.

For more detailed information on cabling options including RS485, transformer-coupled RS-485

and Fiber Optic interfaces, please refer to the following technical note which is available from

Standard Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020

ULANC.

SMSC COM20019I

Page 5

Rev. 09-25-07

DATASHEET

COM20019I-HD相似产品对比

	COM20019I-HD	COM20019ILJP
描述		Network Controller u0026 Processor ICs ARCNET Contrllr

COM20019I-HD

COM20019I-HD在线购买

COM20019I-HD规格参数

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COM20019I-HD相似产品对比

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