74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 2 December 2015
Product data sheet
1. General description
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP)
and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be
stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
(nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ
output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the
circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
V
CC
.
2. Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +80
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC73D
74HC73DB
74HC73PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO14
SSOP14
Description
plastic small outline package; 14 leads; body width 3.9 mm
plastic shrink small outline package; 14 leads; body width
5.3 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
Nexperia
74HC73
Dual JK flip-flop with reset; negative-edge trigger
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC73
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 2 December 2015
2 of 16
Nexperia
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Fig 4.
Logic diagram (one flip-flop)
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO14, SSOP14 and TSSOP14
5.2 Pin description
Table 2.
Symbol
1CP, 2CP
1R, 2R
1K, 2K
V
CC
GND
1Q, 2Q
1Q, 2Q
1J, 2J
Pin description
Pin
1, 5
2, 6
3, 10
4
11
12, 9
13, 8
14, 7
Description
clock input (HIGH-to-LOW edge-triggered); also referred to as nCP
asynchronous reset input (active LOW); also referred to as nR
synchronous K input; also referred to as nK
positive supply voltage
ground (0 V)
true output; also referred to as nQ
complement output; also referred to as nQ
synchronous J input; also referred to as nJ
74HC73
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 2 December 2015
3 of 16
Nexperia
74HC73
Dual JK flip-flop with reset; negative-edge trigger
6. Functional description
Table 3.
Input
nR
L
H
H
H
H
[1]
Function table
[1]
Output
nCP
X
nJ
X
h
l
h
l
nK
X
h
h
l
l
nQ
L
q
L
H
q
nQ
H
q
H
L
q
asynchronous reset
toggle
load 0 (reset)
load 1 (set)
hold (no change)
Operating mode
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO14 package
(T)SSOP14 package
[1]
[2]
[3]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7.0
20
20
25
50
-
+150
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
74HC73
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 2 December 2015
4 of 16
Nexperia
74HC73
Dual JK flip-flop with reset; negative-edge trigger
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
C
ns/V
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
40.0
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
80.0
-
V
V
V
V
V
A
A
pF
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
25
C
Typ Max
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
40 C
to +85
C
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
40 C
to +125
C
Unit
Min
1.5
3.15
4.2
-
-
-
Max
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
3.98 4.32
5.48 5.81
0.15 0.26
0.16 0.26
-
-
3.5
0.1
4.0
-
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
74HC73
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 2 December 2015
5 of 16
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